Reorganize test dir to ensure test of installed pkg
This commit is contained in:
33
tests/lib/simulators/__init__.py
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33
tests/lib/simulators/__init__.py
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from typing import Type, TYPE_CHECKING, List
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if TYPE_CHECKING:
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from ..sim_testcase import SimTestCase
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class Simulator:
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def __init__(self, testcase_cls: 'Type[SimTestCase]' = None, testcase_cls_inst: 'SimTestCase' = None) -> None:
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self.testcase_cls = testcase_cls
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self.testcase_cls_inst = testcase_cls_inst
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@property
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def tb_files(self) -> List[str]:
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files = []
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files.extend(self.testcase_cls.cpuif.get_sim_files())
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files.append("regblock_pkg.sv")
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files.append("regblock.sv")
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files.append("tb.sv")
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return files
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def compile(self) -> None:
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raise NotImplementedError
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def run(self, plusargs:List[str] = None) -> None:
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raise NotImplementedError
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class StubSimulator(Simulator):
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def compile(self) -> None:
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pass
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def run(self, plusargs:List[str] = None) -> None:
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pass
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64
tests/lib/simulators/questa.py
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64
tests/lib/simulators/questa.py
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from typing import List
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import subprocess
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import os
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from . import Simulator
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class Questa(Simulator):
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def compile(self) -> None:
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cmd = [
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"vlog", "-sv", "-quiet", "-l", "build.log",
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"+incdir+%s" % os.path.join(os.path.dirname(__file__), ".."),
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# Use strict LRM conformance
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"-svinputport=net",
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# all warnings are errors
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"-warning", "error",
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# Ignore noisy warning about vopt-time checking of always_comb/always_latch
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"-suppress", "2583",
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]
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# Add source files
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cmd.extend(self.tb_files)
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# Run command!
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subprocess.run(cmd, check=True)
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def run(self, plusargs:List[str] = None) -> None:
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plusargs = plusargs or []
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test_name = self.testcase_cls_inst.request.node.name
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# call vsim
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cmd = [
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"vsim", "-quiet",
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"-voptargs=+acc",
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"-msgmode", "both",
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"-do", "set WildcardFilter [lsearch -not -all -inline $WildcardFilter Memory]",
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"-do", "log -r /*;",
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"-do", "run -all; exit;",
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"-c",
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"-l", "%s.log" % test_name,
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"-wlf", "%s.wlf" % test_name,
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"tb",
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]
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for plusarg in plusargs:
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cmd.append("+" + plusarg)
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subprocess.run(cmd, check=True)
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self.assertSimLogPass("%s.log" % test_name)
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def assertSimLogPass(self, path: str):
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self.testcase_cls_inst.assertTrue(os.path.isfile(path))
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with open(path, encoding="utf-8") as f:
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for line in f:
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if line.startswith("# ** Error"):
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self.testcase_cls_inst.fail(line)
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elif line.startswith("# ** Fatal"):
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self.testcase_cls_inst.fail(line)
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61
tests/lib/simulators/xilinx.py
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61
tests/lib/simulators/xilinx.py
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from typing import List
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import subprocess
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import os
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from . import Simulator
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class Xilinx(Simulator):
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"""
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Don't bother using the Xilinx simulator... Its buggy and extraordinarily slow.
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As observed in v2021.1, clocking block assignments do not seem to actually simulate
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correctly - assignment statements get ignored or the values get mangled.
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Keeping this here in case someday it works better...
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"""
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def compile(self) -> None:
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cmd = [
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"xvlog", "--sv",
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"--include", os.path.join(os.path.dirname(__file__), ".."),
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]
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cmd.extend(self.tb_files)
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subprocess.run(cmd, check=True)
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cmd = [
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"xelab",
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"--timescale", "1ns/1ps",
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"--debug", "all",
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"tb",
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]
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subprocess.run(cmd, check=True)
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def run(self, plusargs:List[str] = None) -> None:
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plusargs = plusargs or []
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test_name = self.testcase_cls_inst.request.node.name
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# call vsim
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cmd = [
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"xsim",
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"--R",
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"--log", "%s.log" % test_name,
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"tb",
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]
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for plusarg in plusargs:
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cmd.append("--testplusarg")
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cmd.append(plusarg)
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subprocess.run(cmd, check=True)
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self.assertSimLogPass("%s.log" % test_name)
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def assertSimLogPass(self, path: str):
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self.testcase_cls_inst.assertTrue(os.path.isfile(path))
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with open(path, encoding="utf-8") as f:
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for line in f:
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if line.startswith("Error:"):
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self.testcase_cls_inst.fail(line)
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elif line.startswith("Fatal:"):
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self.testcase_cls_inst.fail(line)
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