Reorganize test dir to ensure test of installed pkg

tests/test_structural_sw_rw/regblock.rdl

@@ -0,0 +1,34 @@
+addrmap regblock {
+    default sw=rw;
+    default hw=r;
+
+    reg my_reg {
+        field {} a[8] = 0x23;
+        field {} b = 0;
+        field {} c[31:31] = 1;
+    };
+
+    my_reg r0 @0x000;
+    r0.a->reset = 0x42;
+
+    my_reg r1[2][3][4] @0x10 += 8;
+
+    my_reg r2 @0x1000;
+    r2.a->reset = 0x11;
+
+
+    reg subreg {
+        field {} x[7:4] = 1;
+    };
+    regfile subrf {
+        subreg r1[4] @ 0x0 += 4;
+        regfile {
+            subreg r1 @ 0x0;
+            subreg r2[2] @ 0x4 += 4;
+            subreg r3 @ 0xc;
+        } sub[2] @ 0x10 += 0x10;
+        subreg r2[4] @ 0x30 += 4;
+    };
+    subrf sub2[2] @ 0x2000 += 0x40;
+    subreg r3 @ 0x2080;
+};

tests/test_structural_sw_rw/tb_template.sv

@@ -0,0 +1,64 @@
+{% extends "lib/tb_base.sv" %}
+
+{% block seq %}
+    {% sv_line_anchor %}
+    ##1;
+    cb.rst <= '0;
+    ##1;
+
+    // Assert value via frontdoor
+    cpuif.assert_read(0, 32'h8000_0042);
+    for(int i=0; i<2*3*4; i++) begin
+        cpuif.assert_read('h10+i*8, 32'h8000_0023);
+    end
+    cpuif.assert_read('h1000, 32'h8000_0011);
+    for(int i=0; i<33; i++) begin
+        cpuif.assert_read('h2000 +i*4, 32'h0000_0010);
+    end
+
+    // Assert via hwif
+    assert(cb.hwif_out.r0.a.value == 'h42);
+    assert(cb.hwif_out.r0.b.value == 'h0);
+    assert(cb.hwif_out.r0.c.value == 'h1);
+    foreach(cb.hwif_out.r1[x, y, z]) begin
+        assert(cb.hwif_out.r1[x][y][z].a.value == 'h23);
+        assert(cb.hwif_out.r1[x][y][z].b.value == 'h0);
+        assert(cb.hwif_out.r1[x][y][z].c.value == 'h1);
+    end
+    assert(cb.hwif_out.r2.a.value == 'h11);
+    assert(cb.hwif_out.r2.b.value == 'h0);
+    assert(cb.hwif_out.r2.c.value == 'h1);
+
+    // Write values
+    cpuif.write(0, 32'h8000_0002);
+    for(int i=0; i<2*3*4; i++) begin
+        cpuif.write('h10+i*8, i+'h110a);
+    end
+    cpuif.write('h1000, 32'h0000_0000);
+    for(int i=0; i<33; i++) begin
+        cpuif.write('h2000 +i*4, i << 4);
+    end
+
+    // Assert value via frontdoor
+    cpuif.assert_read(0, 32'h8000_0002);
+    for(int i=0; i<2*3*4; i++) begin
+        cpuif.assert_read('h10+i*8, i+'h10a);
+    end
+    cpuif.assert_read('h1000, 32'h0000_0000);
+    for(int i=0; i<33; i++) begin
+        cpuif.assert_read('h2000 +i*4, (i << 4) & 'hF0);
+    end
+
+    // Assert via hwif
+    assert(cb.hwif_out.r0.a.value == 'h02);
+    assert(cb.hwif_out.r0.b.value == 'h0);
+    assert(cb.hwif_out.r0.c.value == 'h1);
+    foreach(cb.hwif_out.r1[x, y, z]) begin
+        assert(cb.hwif_out.r1[x][y][z].a.value == x*12+y*4+z+10);
+        assert(cb.hwif_out.r1[x][y][z].b.value == 'h1);
+        assert(cb.hwif_out.r1[x][y][z].c.value == 'h0);
+    end
+    assert(cb.hwif_out.r2.a.value == 'h0);
+    assert(cb.hwif_out.r2.b.value == 'h0);
+    assert(cb.hwif_out.r2.c.value == 'h0);
+{% endblock %}

tests/test_structural_sw_rw/testcase.py

@@ -0,0 +1,15 @@
+from parameterized import parameterized_class
+
+from ..lib.sim_testcase import SimTestCase
+from ..lib.synth_testcase import SynthTestCase
+from ..lib.test_params import TEST_PARAMS
+
+@parameterized_class(TEST_PARAMS)
+class Test(SimTestCase):
+    def test_dut(self):
+        self.run_test()
+
+@parameterized_class(TEST_PARAMS)
+class TestSynth(SynthTestCase):
+    def test_dut(self):
+        self.run_synth()