diff --git a/src/peakrdl_regblock/cpuif/apb3/apb3_tmpl.sv b/src/peakrdl_regblock/cpuif/apb3/apb3_tmpl.sv
index 4cc23af..33a3663 100644
--- a/src/peakrdl_regblock/cpuif/apb3/apb3_tmpl.sv
+++ b/src/peakrdl_regblock/cpuif/apb3/apb3_tmpl.sv
@@ -1,9 +1,9 @@
 {%- if cpuif.is_interface -%}
 `ifndef SYNTHESIS
     initial begin
-        assert($bits({{cpuif.signal("paddr")}}) >= {{ds.package_name}}::{{ds.module_name.upper()}}_MIN_ADDR_WIDTH)
+        assert_bad_addr_width: assert($bits({{cpuif.signal("paddr")}}) >= {{ds.package_name}}::{{ds.module_name.upper()}}_MIN_ADDR_WIDTH)
             else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits({{cpuif.signal("paddr")}}), {{ds.package_name}}::{{ds.module_name.upper()}}_MIN_ADDR_WIDTH);
-        assert($bits({{cpuif.signal("pwdata")}}) == {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH)
+        assert_bad_data_width: assert($bits({{cpuif.signal("pwdata")}}) == {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH)
             else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits({{cpuif.signal("pwdata")}}), {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH);
     end
 `endif
diff --git a/src/peakrdl_regblock/cpuif/apb4/apb4_tmpl.sv b/src/peakrdl_regblock/cpuif/apb4/apb4_tmpl.sv
index 0152aeb..4293bec 100644
--- a/src/peakrdl_regblock/cpuif/apb4/apb4_tmpl.sv
+++ b/src/peakrdl_regblock/cpuif/apb4/apb4_tmpl.sv
@@ -1,9 +1,9 @@
 {%- if cpuif.is_interface -%}
 `ifndef SYNTHESIS
     initial begin
-        assert($bits({{cpuif.signal("paddr")}}) >= {{ds.package_name}}::{{ds.module_name.upper()}}_MIN_ADDR_WIDTH)
+        assert_bad_addr_width: assert($bits({{cpuif.signal("paddr")}}) >= {{ds.package_name}}::{{ds.module_name.upper()}}_MIN_ADDR_WIDTH)
             else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits({{cpuif.signal("paddr")}}), {{ds.package_name}}::{{ds.module_name.upper()}}_MIN_ADDR_WIDTH);
-        assert($bits({{cpuif.signal("pwdata")}}) == {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH)
+        assert_bad_data_width: assert($bits({{cpuif.signal("pwdata")}}) == {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH)
             else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits({{cpuif.signal("pwdata")}}), {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH);
     end
 `endif
diff --git a/src/peakrdl_regblock/cpuif/avalon/avalon_tmpl.sv b/src/peakrdl_regblock/cpuif/avalon/avalon_tmpl.sv
index a815f9f..fe59b23 100644
--- a/src/peakrdl_regblock/cpuif/avalon/avalon_tmpl.sv
+++ b/src/peakrdl_regblock/cpuif/avalon/avalon_tmpl.sv
@@ -1,9 +1,9 @@
 {%- if cpuif.is_interface -%}
 `ifndef SYNTHESIS
     initial begin
-        assert($bits({{cpuif.signal("address")}}) >= {{cpuif.word_addr_width}})
+        assert_bad_addr_width: assert($bits({{cpuif.signal("address")}}) >= {{cpuif.word_addr_width}})
             else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits({{cpuif.signal("address")}}), {{cpuif.word_addr_width}});
-        assert($bits({{cpuif.signal("writedata")}}) == {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH)
+        assert_bad_data_width: assert($bits({{cpuif.signal("writedata")}}) == {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH)
             else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits({{cpuif.signal("writedata")}}), {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH);
     end
 `endif
diff --git a/src/peakrdl_regblock/cpuif/axi4lite/axi4lite_tmpl.sv b/src/peakrdl_regblock/cpuif/axi4lite/axi4lite_tmpl.sv
index a578718..d89113e 100644
--- a/src/peakrdl_regblock/cpuif/axi4lite/axi4lite_tmpl.sv
+++ b/src/peakrdl_regblock/cpuif/axi4lite/axi4lite_tmpl.sv
@@ -1,9 +1,9 @@
 {%- if cpuif.is_interface -%}
 `ifndef SYNTHESIS
     initial begin
-        assert($bits({{cpuif.signal("araddr")}}) >= {{ds.package_name}}::{{ds.module_name.upper()}}_MIN_ADDR_WIDTH)
+        assert_bad_addr_width: assert($bits({{cpuif.signal("araddr")}}) >= {{ds.package_name}}::{{ds.module_name.upper()}}_MIN_ADDR_WIDTH)
             else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits({{cpuif.signal("araddr")}}), {{ds.package_name}}::{{ds.module_name.upper()}}_MIN_ADDR_WIDTH);
-        assert($bits({{cpuif.signal("wdata")}}) == {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH)
+        assert_bad_data_width: assert($bits({{cpuif.signal("wdata")}}) == {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH)
             else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits({{cpuif.signal("wdata")}}), {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH);
     end
 `endif
diff --git a/src/peakrdl_regblock/module_tmpl.sv b/src/peakrdl_regblock/module_tmpl.sv
index 609b1aa..bad1c21 100644
--- a/src/peakrdl_regblock/module_tmpl.sv
+++ b/src/peakrdl_regblock/module_tmpl.sv
@@ -60,9 +60,9 @@ module {{ds.module_name}}
             if(external_req & ~external_wr_ack & ~external_rd_ack) external_pending <= '1;
             else if(external_wr_ack | external_rd_ack) external_pending <= '0;
             `ifndef SYNTHESIS
-                assert(!external_wr_ack || (external_pending | external_req))
+                assert_bad_ext_wr_ack: assert(!external_wr_ack || (external_pending | external_req))
                     else $error("An external wr_ack strobe was asserted when no external request was active");
-                assert(!external_rd_ack || (external_pending | external_req))
+                assert_bad_ext_rd_ack: assert(!external_rd_ack || (external_pending | external_req))
                     else $error("An external rd_ack strobe was asserted when no external request was active");
             `endif
         end