Move get_always_ff_event() to a more sensible location

src/peakrdl_regblock/cpuif/base.py

@@ -4,7 +4,7 @@ import os
 
 import jinja2 as jj
 
-from ..utils import get_always_ff_event, clog2, is_pow2, roundup_pow2
+from ..utils import clog2, is_pow2, roundup_pow2
 
 if TYPE_CHECKING:
     from ..exporter import RegblockExporter
@@ -51,7 +51,7 @@ class CpuifBase:
 
         context = {
             "cpuif": self,
-            "get_always_ff_event": lambda resetsignal : get_always_ff_event(self.exp.dereferencer, resetsignal),
+            "get_always_ff_event": self.exp.dereferencer.get_always_ff_event,
             "get_resetsignal": self.exp.dereferencer.get_resetsignal,
             "clog2": clog2,
             "is_pow2": is_pow2,

src/peakrdl_regblock/dereferencer.py

@@ -211,7 +211,7 @@ class Dereferencer:
         """
         return self.address_decode.get_external_block_access_strobe(obj)
 
-    def get_resetsignal(self, obj: Optional[SignalNode]) -> str:
+    def get_resetsignal(self, obj: Optional[SignalNode] = None) -> str:
         """
         Returns a normalized active-high reset signal
         """
@@ -224,3 +224,12 @@ class Dereferencer:
 
         # default reset signal
         return "rst"
+
+    def get_always_ff_event(self, resetsignal: Optional[SignalNode] = None) -> str:
+        if resetsignal is None:
+            return "@(posedge clk)"
+        if resetsignal.get_property('async') and resetsignal.get_property('activehigh'):
+            return f"@(posedge clk or posedge {self.get_value(resetsignal)})"
+        elif resetsignal.get_property('async') and not resetsignal.get_property('activehigh'):
+            return f"@(posedge clk or negedge {self.get_value(resetsignal)})"
+        return "@(posedge clk)"

src/peakrdl_regblock/exporter.py

@@ -10,7 +10,6 @@ from .dereferencer import Dereferencer
 from .readback import Readback
 from .identifier_filter import kw_filter as kwf
 
-from .utils import get_always_ff_event
 from .scan_design import DesignScanner
 from .validate_design import DesignValidator
 from .cpuif import CpuifBase
@@ -221,7 +220,7 @@ class RegblockExporter:
             "readback": self.readback,
             "ext_write_acks": ext_write_acks,
             "ext_read_acks": ext_read_acks,
-            "get_always_ff_event": lambda resetsignal : get_always_ff_event(self.dereferencer, resetsignal),
+            "get_always_ff_event": self.dereferencer.get_always_ff_event,
             "retime_read_response": retime_read_response,
             "retime_read_fanin": retime_read_fanin,
             "min_read_latency": self.min_read_latency,

src/peakrdl_regblock/field_logic/generators.py

@@ -7,7 +7,7 @@ from systemrdl.node import RegNode, RegfileNode, MemNode, AddrmapNode
 
 from ..struct_generator import RDLStructGenerator
 from ..forloop_generator import RDLForLoopGenerator
-from ..utils import get_always_ff_event, get_indexed_path
+from ..utils import get_indexed_path
 from ..identifier_filter import kw_filter as kwf
 
 if TYPE_CHECKING:
@@ -228,7 +228,7 @@ class FieldLogicGenerator(RDLForLoopGenerator):
             'extra_combo_signals': extra_combo_signals,
             'conditionals': conditionals,
             'resetsignal': resetsignal,
-            'get_always_ff_event': lambda resetsignal : get_always_ff_event(self.exp.dereferencer, resetsignal),
+            'get_always_ff_event': self.exp.dereferencer.get_always_ff_event,
             'get_value': self.exp.dereferencer.get_value,
             'get_resetsignal': self.exp.dereferencer.get_resetsignal,
             'get_input_identifier': self.exp.hwif.get_input_identifier,
@@ -335,7 +335,7 @@ class FieldLogicGenerator(RDLForLoopGenerator):
             "strb": strb,
             "bslice": bslice,
             "retime": self.field_logic.retime_external_reg,
-            "get_always_ff_event": lambda resetsignal : get_always_ff_event(self.exp.dereferencer, resetsignal),
+            'get_always_ff_event': self.exp.dereferencer.get_always_ff_event,
             "get_resetsignal": self.exp.dereferencer.get_resetsignal,
             "resetsignal": self.exp.top_node.cpuif_reset,
         }
@@ -359,7 +359,7 @@ class FieldLogicGenerator(RDLForLoopGenerator):
             "strb": strb,
             "addr_width": addr_width,
             "retime": retime,
-            "get_always_ff_event": lambda resetsignal : get_always_ff_event(self.exp.dereferencer, resetsignal),
+            'get_always_ff_event': self.exp.dereferencer.get_always_ff_event,
             "get_resetsignal": self.exp.dereferencer.get_resetsignal,
             "resetsignal": self.exp.top_node.cpuif_reset,
         }

src/peakrdl_regblock/readback/__init__.py

@@ -2,7 +2,6 @@ from typing import TYPE_CHECKING
 import math
 
 from .generators import ReadbackAssignmentGenerator
-from ..utils import get_always_ff_event
 
 if TYPE_CHECKING:
     from ..exporter import RegblockExporter
@@ -31,7 +30,7 @@ class Readback:
         context = {
             "array_assignments" : array_assignments,
             "array_size" : array_size,
-            "get_always_ff_event": lambda resetsignal : get_always_ff_event(self.exp.dereferencer, resetsignal),
+            'get_always_ff_event': self.exp.dereferencer.get_always_ff_event,
             "cpuif": self.exp.cpuif,
             "do_fanin_stage": self.do_fanin_stage,
             "has_external_addressable": self.has_external_addressable,

src/peakrdl_regblock/utils.py

@@ -1,15 +1,11 @@
 import re
-from typing import TYPE_CHECKING, Match, Union
+from typing import Match, Union
 
 from systemrdl.rdltypes.references import PropertyReference
-from systemrdl.node import Node, SignalNode, AddrmapNode
+from systemrdl.node import Node, AddrmapNode
 
 from .identifier_filter import kw_filter as kwf
 
-if TYPE_CHECKING:
-    from typing import Optional
-    from .dereferencer import Dereferencer
-
 def get_indexed_path(top_node: Node, target_node: Node) -> str:
     """
     TODO: Add words about indexing and why i'm doing this. Copy from logbook
@@ -33,16 +29,6 @@ def get_indexed_path(top_node: Node, target_node: Node) -> str:
 
     return path
 
-
-def get_always_ff_event(dereferencer: 'Dereferencer', resetsignal: 'Optional[SignalNode]') -> str:
-    if resetsignal is None:
-        return "@(posedge clk)"
-    if resetsignal.get_property('async') and resetsignal.get_property('activehigh'):
-        return f"@(posedge clk or posedge {dereferencer.get_value(resetsignal)})"
-    elif resetsignal.get_property('async') and not resetsignal.get_property('activehigh'):
-        return f"@(posedge clk or negedge {dereferencer.get_value(resetsignal)})"
-    return "@(posedge clk)"
-
 def clog2(n: int) -> int:
     return (n-1).bit_length()
 

src/peakrdl_regblock/write_buffering/implementation_generator.py

@@ -5,7 +5,6 @@ from systemrdl.component import Reg
 from systemrdl.node import RegNode
 
 from ..forloop_generator import RDLForLoopGenerator
-from ..utils import get_always_ff_event
 
 if TYPE_CHECKING:
     from . import WriteBuffering
@@ -54,7 +53,7 @@ class WBufLogicGenerator(RDLForLoopGenerator):
             'node': node,
             'cpuif': self.exp.cpuif,
             'get_resetsignal': self.exp.dereferencer.get_resetsignal,
-            'get_always_ff_event': lambda resetsignal : get_always_ff_event(self.exp.dereferencer, resetsignal),
+            'get_always_ff_event': self.exp.dereferencer.get_always_ff_event,
             'is_own_trigger': is_own_trigger,
         }
         self.add_content(self.template.render(context))

tests/README.md

@@ -7,11 +7,11 @@ Testcases require an installation of the Questa simulator, and for `vlog` & `vsi
 commands to be visible via the PATH environment variable.
 
 *Questa - Intel FPGA Starter Edition* can be downloaded for free from Intel:
-* Go to https://www.intel.com/content/www/us/en/collections/products/fpga/software/downloads.html?edition=pro&s=Newest
+* Go to https://www.intel.com/content/www/us/en/collections/products/fpga/software/downloads.html?edition=pro&q=questa&s=Relevancy
-* Select latest version of *Intel Quartus Prime Pro*
+* Select latest version of Questa
-* Go to the *Individual Files* tab.
 * Download Questa files. (Don't forget part 2!)
 * Install
+    * Be sure to choose "Starter Edition" for the free version.
 * Create an account on https://licensing.intel.com
     * press "Enroll" to register
     * After you confirm your email, go back to this page and press "Enroll" again to finish enrollment
@@ -19,6 +19,9 @@ commands to be visible via the PATH environment variable.
 * Generate a free *Starter Edition* license file for Questa
     * Easiest to use a *fixed* license using your NIC ID (MAC address of your network card via `ifconfig`)
 * Download the license file and point the `LM_LICENSE_FILE` environment variable to the folder which contains it.
+* (optional) Delete Intel libraries to save some disk space
+    * Delete `<install_dir>/questa_fse/intel`
+    * Edit `<install_dir>/questa_fse/modelsim.ini` and remove lines that reference the `intel` libraries
 
 
 ## Vivado (optional)