bslathi19/PeakRDL-regblock
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Refactor exporter class to clean up the mess of random variables

Browse Source
This commit is contained in:
Alex Mykyta
2023-05-12 23:44:09 -07:00
parent 5b3cdd9d7a
commit 5e76956618
19 changed files with 210 additions and 217 deletions
Download Patch File Download Diff File Expand all files Collapse all files

50
src/peakrdl_regblock/module_tmpl.sv
View File

@@ -1,11 +1,11 @@
// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator
// https://github.com/SystemRDL/PeakRDL-regblock
module {{module_name}} (
module {{ds.module_name}} (
input wire clk,
input wire rst,
{%- for signal in user_out_of_hier_signals %}
{%- for signal in ds.out_of_hier_signals.values() %}
{%- if signal.width == 1 %}
input wire {{kwf(signal.inst_name)}},
{%- else %}
@@ -40,7 +40,7 @@ module {{module_name}} (
{{cpuif.get_implementation()|indent}}
logic cpuif_req_masked;
{%- if has_external_addressable %}
{%- if ds.has_external_addressable %}
logic external_req;
logic external_pending;
logic external_wr_ack;
@@ -54,9 +54,9 @@ module {{module_name}} (
end
end
{%- endif %}
{% if min_read_latency == min_write_latency %}
{% if ds.min_read_latency == ds.min_write_latency %}
// Read & write latencies are balanced. Stalls not required
{%- if has_external_addressable %}
{%- if ds.has_external_addressable %}
// except if external
assign cpuif_req_stall_rd = external_pending;
assign cpuif_req_stall_wr = external_pending;
@@ -64,9 +64,9 @@ module {{module_name}} (
assign cpuif_req_stall_rd = '0;
assign cpuif_req_stall_wr = '0;
{%- endif %}
{%- elif min_read_latency > min_write_latency %}
{%- elif ds.min_read_latency > ds.min_write_latency %}
// Read latency > write latency. May need to delay next write that follows a read
logic [{{min_read_latency - min_write_latency - 1}}:0] cpuif_req_stall_sr;
logic [{{ds.min_read_latency - ds.min_write_latency - 1}}:0] cpuif_req_stall_sr;
always_ff {{get_always_ff_event(cpuif.reset)}} begin
if({{get_resetsignal(cpuif.reset)}}) begin
cpuif_req_stall_sr <= '0;
@@ -76,7 +76,7 @@ module {{module_name}} (
cpuif_req_stall_sr <= (cpuif_req_stall_sr >> 'd1);
end
end
{%- if has_external_addressable %}
{%- if ds.has_external_addressable %}
assign cpuif_req_stall_rd = external_pending;
assign cpuif_req_stall_wr = cpuif_req_stall_sr[0] | external_pending;
{%- else %}
@@ -85,7 +85,7 @@ module {{module_name}} (
{%- endif %}
{%- else %}
// Write latency > read latency. May need to delay next read that follows a write
logic [{{min_write_latency - min_read_latency - 1}}:0] cpuif_req_stall_sr;
logic [{{ds.min_write_latency - ds.min_read_latency - 1}}:0] cpuif_req_stall_sr;
always_ff {{get_always_ff_event(cpuif.reset)}} begin
if({{get_resetsignal(cpuif.reset)}}) begin
cpuif_req_stall_sr <= '0;
@@ -95,7 +95,7 @@ module {{module_name}} (
cpuif_req_stall_sr <= (cpuif_req_stall_sr >> 'd1);
end
end
{%- if has_external_addressable %}
{%- if ds.has_external_addressable %}
assign cpuif_req_stall_rd = cpuif_req_stall_sr[0] | external_pending;
assign cpuif_req_stall_wr = external_pending;
{%- else %}
@@ -112,10 +112,10 @@ module {{module_name}} (
//--------------------------------------------------------------------------
{{address_decode.get_strobe_struct()|indent}}
decoded_reg_strb_t decoded_reg_strb;
{%- if has_external_addressable %}
{%- if ds.has_external_addressable %}
logic decoded_strb_is_external;
{% endif %}
{%- if has_external_block %}
{%- if ds.has_external_block %}
logic [{{cpuif.addr_width-1}}:0] decoded_addr;
{% endif %}
logic decoded_req;
@@ -124,25 +124,25 @@ module {{module_name}} (
logic [{{cpuif.data_width-1}}:0] decoded_wr_biten;
always_comb begin
{%- if has_external_addressable %}
{%- if ds.has_external_addressable %}
automatic logic is_external = '0;
{% endif %}
{{address_decode.get_implementation()|indent(8)}}
{%- if has_external_addressable %}
{%- if ds.has_external_addressable %}
decoded_strb_is_external = is_external;
external_req = is_external;
{% endif %}
end
// Pass down signals to next stage
{%- if has_external_block %}
{%- if ds.has_external_block %}
assign decoded_addr = cpuif_addr;
{% endif %}
assign decoded_req = cpuif_req_masked;
assign decoded_req_is_wr = cpuif_req_is_wr;
assign decoded_wr_data = cpuif_wr_data;
assign decoded_wr_biten = cpuif_wr_biten;
{% if has_writable_msb0_fields %}
{% if ds.has_writable_msb0_fields %}
// bitswap for use by fields with msb0 ordering
logic [{{cpuif.data_width-1}}:0] decoded_wr_data_bswap;
logic [{{cpuif.data_width-1}}:0] decoded_wr_biten_bswap;
@@ -150,7 +150,7 @@ module {{module_name}} (
assign decoded_wr_biten_bswap = {<<{decoded_wr_biten}};
{%- endif %}
{%- if has_buffered_write_regs %}
{%- if ds.has_buffered_write_regs %}
//--------------------------------------------------------------------------
// Write double-buffers
@@ -168,7 +168,7 @@ module {{module_name}} (
{{field_logic.get_implementation()|indent}}
{%- if has_buffered_read_regs %}
{%- if ds.has_buffered_read_regs %}
//--------------------------------------------------------------------------
// Read double-buffers
@@ -181,7 +181,7 @@ module {{module_name}} (
//--------------------------------------------------------------------------
// Write response
//--------------------------------------------------------------------------
{%- if has_external_addressable %}
{%- if ds.has_external_addressable %}
always_comb begin
automatic logic wr_ack;
wr_ack = '0;
@@ -198,7 +198,7 @@ module {{module_name}} (
//--------------------------------------------------------------------------
// Readback
//--------------------------------------------------------------------------
{%- if has_external_addressable %}
{%- if ds.has_external_addressable %}
logic readback_external_rd_ack_c;
always_comb begin
automatic logic rd_ack;
@@ -208,7 +208,7 @@ module {{module_name}} (
end
logic readback_external_rd_ack;
{%- if retime_read_fanin %}
{%- if ds.retime_read_fanin %}
always_ff {{get_always_ff_event(cpuif.reset)}} begin
if({{get_resetsignal(cpuif.reset)}}) begin
readback_external_rd_ack <= '0;
@@ -227,17 +227,17 @@ module {{module_name}} (
logic readback_done;
logic [{{cpuif.data_width-1}}:0] readback_data;
{{readback.get_implementation()|indent}}
{% if retime_read_response %}
{% if ds.retime_read_response %}
always_ff {{get_always_ff_event(cpuif.reset)}} begin
if({{get_resetsignal(cpuif.reset)}}) begin
cpuif_rd_ack <= '0;
cpuif_rd_data <= '0;
cpuif_rd_err <= '0;
{%- if has_external_addressable %}
{%- if ds.has_external_addressable %}
external_rd_ack <= '0;
{%- endif %}
end else begin
{%- if has_external_addressable %}
{%- if ds.has_external_addressable %}
external_rd_ack <= readback_external_rd_ack;
cpuif_rd_ack <= readback_done | readback_external_rd_ack;
{%- else %}
@@ -248,7 +248,7 @@ module {{module_name}} (
end
end
{% else %}
{%- if has_external_addressable %}
{%- if ds.has_external_addressable %}
assign external_rd_ack = readback_external_rd_ack;
assign cpuif_rd_ack = readback_done | readback_external_rd_ack;
{%- else %}