Add interrupt tests!

docs/dev_notes/Validation Needed

@@ -105,12 +105,13 @@ X sticky=true + "(posedge|negedge|bothedge) intr"
 X we/wel + implied or explicit "sticky"/"stickybit"
     we/wel modifier doesn't make sense here.
 
-! hwclr/hwset/we/wel probably shouldn't be able to reference itself
-    y->hwclr = y;
-    y->we = y;
-    ... it works, but should it be allowed? Seems like user-error
+X sticky/stickybit shall be hw writable
 
-! counter field that saturates should not set overflow
+X Illegal to use enable/mask/haltenable/haltmask on non-intr fields
+
+X incrwidth/decrwidth must be between 1 and the width of the counter
+
+X counter field that saturates should not set overflow
     counter; incrsaturate; overflow;
     counter; decrsaturate; underflow;
 
@@ -119,11 +120,10 @@ X we/wel + implied or explicit "sticky"/"stickybit"
 
     Same goes to prop references to overflow/underflow
 
-! incrwidth/decrwidth must be between 1 and the width of the counter
-
-! Illegal to use enable/mask/haltenable/haltmask on non-intr fields
-
-! sticky/stickybit shall be hw writable
+! hwclr/hwset/we/wel probably shouldn't be able to reference itself
+    y->hwclr = y;
+    y->we = y;
+    ... it works, but should it be allowed? Seems like user-error
 
 ================================================================================
 Things that need validation by this exporter
@@ -148,7 +148,7 @@ X Warn/error on any signal with cpuif_reset set, that is not in the top-level
 
 ! async data signals
     Only supporting async signals if they are exclusively used in resets.
-    Anyhting else declared as "async" shall emit a warning that it is ignored
+    Anything else declared as "async" shall emit a warning that it is ignored
     I have zero interest in implementing resynchronizers
 
 ! Error if a property references a non-signal component, or property reference from

docs/dev_notes/template-layers/4-fields

@@ -53,7 +53,7 @@ TODO:
     Provide a mechanism for users to extend/override field behavior
 
 TODO:
-    Does the endinness the user sets matter anywhere?
+    Does the endianness the user sets matter anywhere?
 
 Implementation
     Makes sense to use a listener class
@@ -63,7 +63,7 @@ Be sure to skip alias registers
 --------------------------------------------------------------------------------
 
 NextStateConditional Class
-    Decribes a single conditional action that determines the next state of a field
+    Describes a single conditional action that determines the next state of a field
     Provides information to generate the following content:
         if(<conditional>) begin
             <assignments>
@@ -110,22 +110,22 @@ FieldBuilder Class
         NextStateConditional objects are stored in a dictionary as follows:
             _conditionals {
                 assignment_precedence: [
-                    conditional_option_3,
-                    conditional_option_2,
                     conditional_option_1,
+                    conditional_option_2,
+                    conditional_option_3,
                 ]
             }
 
     add_conditional(self, conditional, assignment_precedence):
         Inserts the NextStateConditional into the given assignment precedence bin
-        The last one added to a precedence bin is first in that bin's search order
+        The first one added to a precedence bin is first in that bin's search order
 
     init_conditionals(self) -> None:
         Called from __init__.
         loads all possible conditionals into self.conditionals list
         This function is to provide a hook for the user to add their own.
 
-        Do not do fancy class intospection. Load them explicitly by name like so:
+        Do not do fancy class introspection. Load them explicitly by name like so:
             self.add_conditional(MyNextState(), AssignmentPrecedence.SW_ACCESS)
 
         If user wants to extend this class, they can pile onto the bins of conditionals freely!

docs/index.rst

@@ -44,6 +44,7 @@ Links
    :hidden:
    :caption: CPU Interfaces
 
+   cpuif/addressing
    cpuif/apb3
    cpuif/advanced
 

docs/props/field.rst

@@ -402,46 +402,113 @@ that an interrupt is active. This is an or-reduction of all interrupt fields
 after applying the appropriate ``enable`` or ``mask`` to the field value.
 
 level (default)
-    |EX|
+    |OK|
 
-    Interrupt is level-sensitive.
+    Interrupt is level-sensitive. If a bit on the field's ``hwif_in..next`` input
+    is '1', it will trigger an interrupt event.
 
 posedge
-    |EX|
+    |OK|
+
+    If a bit on the field's ``hwif_in..next`` input transitions from '0' to '1',
+    it will trigger an interrupt event. This transition shall still be synchronous
+    to the register block's clock.
 
 negedge
-    |EX|
+    |OK|
+
+    If a bit on the field's ``hwif_in..next`` input transitions from '1' to '0',
+    it will trigger an interrupt event. This transition shall still be synchronous
+    to the register block's clock.
 
 bothedge
-    |EX|
+    |OK|
+
+    If a bit on the field's ``hwif_in..next`` input transitions from '0' to '1' or '1' to '0',
+    it will trigger an interrupt event. This transition shall still be synchronous
+    to the register block's clock.
 
 nonsticky
-    |EX|
+    |OK|
 
 
 enable
 ^^^^^^
-|EX|
+|OK|
+
+Reference to a field or signal that, if set to 1, define which bits in the field
+are used to assert an interrupt.
+
 
 mask
 ^^^^
-|EX|
+|OK|
+
+Reference to a field or signal that, if set to 1, define which bits in the field
+are *not* used to assert an interrupt.
+
 
 haltenable
 ^^^^^^^^^^
-|EX|
+|OK|
+
+Reference to a field or signal that, if set to 1, define which bits in the field
+are used to assert the halt output.
+
+If this property is set, the enclosing register will infer a ``hwif_out..halt`` output.
+
 
 haltmask
 ^^^^^^^^
-|EX|
+|OK|
+
+Reference to a field or signal that, if set to 1, define which bits in the field
+are *not* used to assert the halt output.
+
+If this property is set, the enclosing register will infer a ``hwif_out..halt`` output.
 
-sticky
-^^^^^^
-|EX|
 
 stickybit
 ^^^^^^^^^
-|EX|
+|OK|
+
+When an interrupt trigger occurs, a stickybit field will set the corresponding
+bit to '1' and hold it until it is cleared by a software access.
+
+The interrupt trigger depends on the interrupt type. By default, interrupts are
+level-sensitive, but the interrupt modifiers allow for edge-sensitive triggers as
+well.
+
+The waveform below demonstrates a level-sensitive interrupt:
+
+.. wavedrom::
+
+    {
+        signal: [
+            {name: 'clk',                 wave: 'p.....'},
+            {name: 'hwif_in..next',       wave: '010...'},
+            {name: '<field value>',       wave: '0.1...'}
+        ]
+    }
+
+
+sticky
+^^^^^^
+|OK|
+
+Unlike ``stickybit`` fields, a sticky field will latch an entire value. The
+value is latched as soon as ``hwif_in..next`` is nonzero, and is held until the
+field contents are cleared back to 0 by a software access.
+
+.. wavedrom::
+
+    {
+        signal: [
+            {name: 'clk',                 wave: 'p.....'},
+            {name: 'hwif_in..next',       wave: '23.22.', data: [0,10,20,30]},
+            {name: '<field value>',       wave: '2.3...', data: [0, 10]}
+        ]
+    }
 
 
 --------------------------------------------------------------------------------

docs/props/rhs_props.rst

@@ -206,8 +206,12 @@ Register
 
 reg -> intr
 ^^^^^^^^^^^
-|EX|
+|OK|
+
+References the register's ``hwif_out..intr`` signal.
 
 reg -> halt
 ^^^^^^^^^^^
-|EX|
+|OK|
+
+References the register's ``hwif_out..halt`` signal.