bslathi19/PeakRDL-regblock
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Implement new SVInt object to defer literal expansion and allow bit-fiddling operations. Fix invalid bit-slicing of literals if field reset value is a constant. #71

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This commit is contained in:
Alex Mykyta
2023-10-24 22:50:41 -07:00
parent b5b1ba790e
commit 62518b318b
14 changed files with 147 additions and 62 deletions
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19
src/peakrdl_regblock/field_logic/__init__.py
View File

@@ -1,4 +1,4 @@
from typing import TYPE_CHECKING
from typing import TYPE_CHECKING, Union
from systemrdl.rdltypes import PrecedenceType, InterruptType
@@ -11,6 +11,7 @@ from . import hw_set_clr
from . import hw_interrupts
from ..utils import get_indexed_path
from ..sv_int import SVInt
from .generators import CombinationalStructGenerator, FieldStorageStructGenerator, FieldLogicGenerator
@@ -99,12 +100,12 @@ class FieldLogic:
"""
prop_value = field.get_property('incr')
if prop_value:
return self.exp.dereferencer.get_value(prop_value)
return str(self.exp.dereferencer.get_value(prop_value))
# unset by the user, points to the implied input signal
return self.exp.hwif.get_implied_prop_input_identifier(field, "incr")
def get_counter_incrvalue(self, field: 'FieldNode') -> str:
def get_counter_incrvalue(self, field: 'FieldNode') -> Union[SVInt, str]:
"""
Return the string that represents the field's increment value
"""
@@ -115,7 +116,7 @@ class FieldLogic:
return self.exp.hwif.get_implied_prop_input_identifier(field, "incrvalue")
return "1'b1"
def get_counter_incrsaturate_value(self, field: 'FieldNode') -> str:
def get_counter_incrsaturate_value(self, field: 'FieldNode') -> Union[SVInt, str]:
prop_value = field.get_property('incrsaturate')
if prop_value is True:
return self.exp.dereferencer.get_value(2**field.width - 1, field.width)
@@ -127,7 +128,7 @@ class FieldLogic:
"""
return field.get_property('incrsaturate') is not False
def get_counter_incrthreshold_value(self, field: 'FieldNode') -> str:
def get_counter_incrthreshold_value(self, field: 'FieldNode') -> Union[SVInt, str]:
prop_value = field.get_property('incrthreshold')
if isinstance(prop_value, bool):
# No explicit value set. use max
@@ -140,12 +141,12 @@ class FieldLogic:
"""
prop_value = field.get_property('decr')
if prop_value:
return self.exp.dereferencer.get_value(prop_value)
return str(self.exp.dereferencer.get_value(prop_value))
# unset by the user, points to the implied input signal
return self.exp.hwif.get_implied_prop_input_identifier(field, "decr")
def get_counter_decrvalue(self, field: 'FieldNode') -> str:
def get_counter_decrvalue(self, field: 'FieldNode') -> Union[SVInt, str]:
"""
Return the string that represents the field's decrement value
"""
@@ -156,7 +157,7 @@ class FieldLogic:
return self.exp.hwif.get_implied_prop_input_identifier(field, "decrvalue")
return "1'b1"
def get_counter_decrsaturate_value(self, field: 'FieldNode') -> str:
def get_counter_decrsaturate_value(self, field: 'FieldNode') -> Union[SVInt, str]:
prop_value = field.get_property('decrsaturate')
if prop_value is True:
return f"{field.width}'d0"
@@ -168,7 +169,7 @@ class FieldLogic:
"""
return field.get_property('decrsaturate') is not False
def get_counter_decrthreshold_value(self, field: 'FieldNode') -> str:
def get_counter_decrthreshold_value(self, field: 'FieldNode') -> Union[SVInt, str]:
prop_value = field.get_property('decrthreshold')
if isinstance(prop_value, bool):
# No explicit value set. use min

4
src/peakrdl_regblock/field_logic/hw_set_clr.py
View File

@@ -17,7 +17,7 @@ class HWSet(NextStateConditional):
identifier = self.exp.hwif.get_implied_prop_input_identifier(field, "hwset")
else:
# signal or field
identifier = self.exp.dereferencer.get_value(prop)
identifier = str(self.exp.dereferencer.get_value(prop))
return identifier
def get_assignments(self, field: 'FieldNode') -> List[str]:
@@ -50,7 +50,7 @@ class HWClear(NextStateConditional):
identifier = self.exp.hwif.get_implied_prop_input_identifier(field, "hwclr")
else:
# signal or field
identifier = self.exp.dereferencer.get_value(prop)
identifier = str(self.exp.dereferencer.get_value(prop))
return identifier
def get_assignments(self, field: 'FieldNode') -> List[str]:

6
src/peakrdl_regblock/field_logic/hw_write.py
View File

@@ -24,7 +24,7 @@ class AlwaysWrite(NextStateConditional):
def get_assignments(self, field: 'FieldNode') -> List[str]:
hwmask = field.get_property('hwmask')
hwenable = field.get_property('hwenable')
I = self.exp.hwif.get_input_identifier(field)
I = str(self.exp.hwif.get_input_identifier(field))
R = self.exp.field_logic.get_storage_identifier(field)
if hwmask is not None:
M = self.exp.dereferencer.get_value(hwmask)
@@ -55,7 +55,7 @@ class WEWrite(AlwaysWrite):
identifier = self.exp.hwif.get_implied_prop_input_identifier(field, "we")
else:
# signal or field
identifier = self.exp.dereferencer.get_value(prop)
identifier = str(self.exp.dereferencer.get_value(prop))
return identifier
class WELWrite(AlwaysWrite):
@@ -73,5 +73,5 @@ class WELWrite(AlwaysWrite):
identifier = self.exp.hwif.get_implied_prop_input_identifier(field, "wel")
else:
# signal or field
identifier = self.exp.dereferencer.get_value(prop)
identifier = str(self.exp.dereferencer.get_value(prop))
return f"!{identifier}"