Implement new SVInt object to defer literal expansion and allow bit-fiddling operations. Fix invalid bit-slicing of literals if field reset value is a constant. #71

src/peakrdl_regblock/read_buffering/__init__.py

@@ -1,10 +1,11 @@
-from typing import TYPE_CHECKING
+from typing import TYPE_CHECKING, Union
 
-from systemrdl.node import AddrmapNode, RegNode, FieldNode, SignalNode
+from systemrdl.node import AddrmapNode, RegNode, SignalNode
 
 from .storage_generator import RBufStorageStructGenerator
 from .implementation_generator import RBufLogicGenerator
 from ..utils import get_indexed_path
+from ..sv_int import SVInt
 
 if TYPE_CHECKING:
     from ..exporter import RegblockExporter
@@ -47,12 +48,12 @@ class ReadBuffering:
         elif isinstance(trigger, SignalNode):
             s = self.exp.dereferencer.get_value(trigger)
             if trigger.get_property('activehigh'):
-                return s
+                return str(s)
             else:
                 return f"~{s}"
         else:
             # Trigger is a field or propref bit
-            return self.exp.dereferencer.get_value(trigger)
+            return str(self.exp.dereferencer.get_value(trigger))
 
     def get_rbuf_data(self, node: RegNode) -> str:
         return "rbuf_storage." + get_indexed_path(self.top_node, node) + ".data"