bslathi19/PeakRDL-regblock
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Implement new SVInt object to defer literal expansion and allow bit-fiddling operations. Fix invalid bit-slicing of literals if field reset value is a constant. #71

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Alex Mykyta
2023-10-24 22:50:41 -07:00
parent b5b1ba790e
commit 62518b318b
14 changed files with 147 additions and 62 deletions
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20
src/peakrdl_regblock/readback/generators.py
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@@ -5,6 +5,8 @@ from systemrdl.walker import WalkerAction
from ..forloop_generator import RDLForLoopGenerator, LoopBody
from ..utils import do_bitswap, do_slice
if TYPE_CHECKING:
from ..exporter import RegblockExporter
@@ -147,7 +149,7 @@ class ReadbackAssignmentGenerator(RDLForLoopGenerator):
value = self.exp.dereferencer.get_value(field)
if field.msb < field.lsb:
# Field gets bitswapped since it is in [low:high] orientation
value = f"{{<<{{{value}}}}}"
value = do_bitswap(value)
self.add_content(f"assign readback_array[{self.current_offset_str}][{field.high}:{field.low}] = {rd_strb} ? {value} : '0;")
@@ -223,9 +225,9 @@ class ReadbackAssignmentGenerator(RDLForLoopGenerator):
f_low = field.width - 1 - f_low
f_high = field.width - 1 - f_high
f_low, f_high = f_high, f_low
value = f"{{<<{{{self.exp.dereferencer.get_value(field)}[{f_high}:{f_low}]}}}}"
value = do_bitswap(do_slice(self.exp.dereferencer.get_value(field), f_high, f_low))
else:
value = self.exp.dereferencer.get_value(field) + f"[{f_high}:{f_low}]"
value = do_slice(self.exp.dereferencer.get_value(field), f_high, f_low)
self.add_content(f"assign readback_array[{self.current_offset_str}][{r_high}:{r_low}] = {rd_strb} ? {value} : '0;")
bidx = accesswidth
@@ -234,7 +236,7 @@ class ReadbackAssignmentGenerator(RDLForLoopGenerator):
value = self.exp.dereferencer.get_value(field)
if field.msb < field.lsb:
# Field gets bitswapped since it is in [low:high] orientation
value = f"{{<<{{{value}}}}}"
value = do_bitswap(value)
self.add_content(f"assign readback_array[{self.current_offset_str}][{field.high}:{field.low}] = {rd_strb} ? {value} : '0;")
bidx = field.high + 1
@@ -299,7 +301,7 @@ class ReadbackAssignmentGenerator(RDLForLoopGenerator):
value = self.exp.dereferencer.get_value(field)
if field.msb < field.lsb:
# Field gets bitswapped since it is in [low:high] orientation
value = f"{{<<{{{value}}}}}"
value = do_bitswap(value)
self.add_content(f"assign readback_array[{self.current_offset_str}][{high}:{low}] = {rd_strb} ? {value} : '0;")
@@ -328,9 +330,9 @@ class ReadbackAssignmentGenerator(RDLForLoopGenerator):
f_high = field.width - 1 - f_high
f_low, f_high = f_high, f_low
value = f"{{<<{{{self.exp.dereferencer.get_value(field)}[{f_high}:{f_low}]}}}}"
value = do_bitswap(do_slice(self.exp.dereferencer.get_value(field), f_high, f_low))
else:
value = self.exp.dereferencer.get_value(field) + f"[{f_high}:{f_low}]"
value = do_slice(self.exp.dereferencer.get_value(field), f_high, f_low)
self.add_content(f"assign readback_array[{self.current_offset_str}][{r_high}:{r_low}] = {rd_strb} ? {value} : '0;")
@@ -358,9 +360,9 @@ class ReadbackAssignmentGenerator(RDLForLoopGenerator):
f_high = field.width - 1 - f_high
f_low, f_high = f_high, f_low
value = f"{{<<{{{self.exp.dereferencer.get_value(field)}[{f_high}:{f_low}]}}}}"
value = do_bitswap(do_slice(self.exp.dereferencer.get_value(field), f_high, f_low))
else:
value = self.exp.dereferencer.get_value(field) + f"[{f_high}:{f_low}]"
value = do_slice(self.exp.dereferencer.get_value(field), f_high, f_low)
self.add_content(f"assign readback_array[{self.current_offset_str}][{r_high}:{r_low}] = {rd_strb} ? {value} : '0;")