Implement new SVInt object to defer literal expansion and allow bit-fiddling operations. Fix invalid bit-slicing of literals if field reset value is a constant. #71

tests/test_wide_regs/regblock.rdl

@@ -90,4 +90,22 @@ addrmap top {
     } counter_reg;
     counter_reg.f1_cnt->incr = r_reg2.f1->swacc;
     counter_reg.f2_cnt->incr = r_reg2.f2->swacc;
+
+    reg {
+        regwidth = 32;
+        accesswidth = 16;
+        default sw=r;
+        default hw=r;
+
+        field {} f1[31:0] = 0x1234_5678;
+    } r_reg3;
+
+    reg {
+        regwidth = 32;
+        accesswidth = 16;
+        default sw=r;
+        default hw=r;
+
+        field {} f1[0:31] = 0x1234_5678;
+    } r_reg4;
 };

tests/test_wide_regs/tb_template.sv

@@ -108,4 +108,14 @@
     // counter_reg
     cpuif.assert_read('h30, 16'h0204);
 
+    // r_reg3
+    cpuif.assert_read('h34, 16'h5678);
+    cpuif.assert_read('h36, 16'h1234);
+    assert(cb.hwif_out.r_reg3.f1.value == 32'h12345678);
+
+    // r_reg4
+    cpuif.assert_read('h38, 16'h2C48);
+    cpuif.assert_read('h3A, 16'h1E6A);
+    assert(cb.hwif_out.r_reg4.f1.value == 32'h12345678);
+
 {% endblock %}