diff --git a/README.md b/README.md
index 4fdb519..8b554c1 100644
--- a/README.md
+++ b/README.md
@@ -9,4 +9,4 @@ Compile SystemRDL into a SystemVerilog control/status register (CSR) block.
 For the command line tool, see the [PeakRDL project](https://peakrdl.readthedocs.io).
 
 ## Documentation
-See the [PeakRDL-regblock Documentation](http://peakrdl-regblock.readthedocs.io) for more details
+See the [PeakRDL-regblock Documentation](https://peakrdl-regblock.readthedocs.io) for more details
diff --git a/docs/index.rst b/docs/index.rst
index d072dbc..f17ceb7 100644
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -25,6 +25,13 @@ The easiest way to use PeakRDL-regblock is via the  `PeakRDL command line tool <
     peakrdl regblock atxmega_spi.rdl -o regblock/ --cpuif axi4-lite
 
 
+Looking for VHDL?
+-----------------
+This project generates SystemVerilog RTL. If you prefer using VHDL, check out
+the sister project which aims to be a feature-equivalent fork of
+PeakRDL-regblock: `PeakRDL-regblock-VHDL <https://peakrdl-regblock-vhdl.readthedocs.io>`_
+
+
 Links
 -----