diff --git a/docs/conf.py b/docs/conf.py
index eb8ead9..e4087b8 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -12,7 +12,7 @@
 #
 import os
 import sys
-sys.path.insert(0, os.path.abspath('..'))
+sys.path.insert(0, os.path.abspath('../src/'))
 
 import datetime
 
diff --git a/docs/index.rst b/docs/index.rst
index 0b7b18b..491f485 100644
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -21,7 +21,7 @@ Install from `PyPi`_ using pip
 
 .. code-block:: bash
 
-   python3 -m pip install peakrdl-regblock
+    python3 -m pip install peakrdl-regblock
 
 .. _PyPi: https://pypi.org/project/peakrdl-regblock
 
@@ -34,35 +34,35 @@ Below is a simple example that demonstrates how to generate a SystemVerilog
 implementation from SystemRDL source.
 
 .. code-block:: python
-   :emphasize-lines: 2-3, 23-27
+    :emphasize-lines: 2-3, 23-27
 
-   from systemrdl import RDLCompiler, RDLCompileError
-   from peakrdl.regblock import RegblockExporter
-   from peakrdl.regblock.cpuif.apb3 import APB3_Cpuif
+    from systemrdl import RDLCompiler, RDLCompileError
+    from peakrdl.regblock import RegblockExporter
+    from peakrdl.regblock.cpuif.apb3 import APB3_Cpuif
 
-   input_files = [
-      "PATH/TO/my_register_block.rdl"
-   ]
+    input_files = [
+        "PATH/TO/my_register_block.rdl"
+    ]
 
-   # Create an instance of the compiler
-   rdlc = RDLCompiler()
-   try:
-      # Compile your RDL files
-      for input_file in input_files:
-         rdlc.compile_file(input_file)
+    # Create an instance of the compiler
+    rdlc = RDLCompiler()
+    try:
+        # Compile your RDL files
+        for input_file in input_files:
+            rdlc.compile_file(input_file)
 
-      # Elaborate the design
-      root = rdlc.elaborate()
-   except RDLCompileError:
-      # A compilation error occurred. Exit with error code
-      sys.exit(1)
+        # Elaborate the design
+        root = rdlc.elaborate()
+    except RDLCompileError:
+        # A compilation error occurred. Exit with error code
+        sys.exit(1)
 
-   # Export a SystemVerilog implementation
-   exporter = RegblockExporter()
-   exporter.export(
-      root, "path/to/output_dir",
-      cpuif_cls=APB3_Cpuif
-   )
+    # Export a SystemVerilog implementation
+    exporter = RegblockExporter()
+    exporter.export(
+        root, "path/to/output_dir",
+        cpuif_cls=APB3_Cpuif
+    )
 
 
 Links
@@ -77,31 +77,31 @@ Links
 
 
 .. toctree::
-   :hidden:
+    :hidden:
 
-   self
-   architecture
-   hwif
-   api
-   limitations
+    self
+    architecture
+    hwif
+    api
+    limitations
 
 .. toctree::
-   :hidden:
-   :caption: CPU Interfaces
+    :hidden:
+    :caption: CPU Interfaces
 
-   cpuif/introduction
-   cpuif/apb3
-   cpuif/axi4lite
-   cpuif/passthrough
-   cpuif/internal_protocol
-   cpuif/customizing
+    cpuif/introduction
+    cpuif/apb3
+    cpuif/axi4lite
+    cpuif/passthrough
+    cpuif/internal_protocol
+    cpuif/customizing
 
 .. toctree::
-   :hidden:
-   :caption: Property Support
+    :hidden:
+    :caption: Property Support
 
-   props/field
-   props/reg
-   props/addrmap
-   props/signal
-   props/rhs_props
+    props/field
+    props/reg
+    props/addrmap
+    props/signal
+    props/rhs_props