Add support for cpuif that have write strobes

docs/cpuif/internal_protocol.rst

@@ -34,6 +34,10 @@ cpuif_wr_data
     Data to be written for the write transfer. This signal is ignored for read
     transfers.
 
+cpuif_wr_biten
+    Active-high bit-level write-enable strobes.
+    Only asserted bit positions will change the register value during a write transfer.
+
 cpuif_req_stall_rd
     If asserted, and the next pending request is a read operation, then the
     transfer will not be accepted until this signal is deasserted.

docs/dev_notes/Validation Needed

@@ -173,6 +173,10 @@ X Do not allow unaligned addresses
 ! Error if a property references a non-signal component, or property reference from
     outside the export hierarchy
 
+! Error if a property is a reference to something that is external, or enclosed
+  in an external component.
+  Limit this check to child nodes inside the export hierarchy
+
 ! Add warning for sticky race condition
     stickybit and other similar situations generally should use hw precedence.
     Emit a warning as appropriate