bslathi19/PeakRDL-regblock
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

bump version

Browse Source
This commit is contained in:
Alex Mykyta
2022-09-23 21:01:11 -07:00
parent 0a6a531c44
commit 6fa5031ada
3 changed files with 11 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
docs/props/signal.rst
View File

@@ -9,6 +9,8 @@ activehigh/activelow
--------------------
|OK|
Only relevant for signals used as resets. Defines the reset signal's polarity.
sync/async
----------
|OK|
@@ -20,6 +22,12 @@ cpuif_reset
-----------
|OK|
Specify that this signal shall be used as alternate reset signal for the CPU
interface for this regblock.
field_reset
-----------
|OK|
Specify that this signal is used as an alternate reset signal for all fields
instantiated in sub-hierarchies relative to this signal.