From 746f6cb020702fef2264f488427fc4ccfe4758b9 Mon Sep 17 00:00:00 2001 From: Alex Mykyta Date: Wed, 16 Mar 2022 20:53:55 -0700 Subject: [PATCH] Doc fixes. Add banner to output --- docs/architecture.rst | 2 +- docs/cpuif/apb3.rst | 4 ++-- docs/cpuif/axi4lite.rst | 4 ++-- docs/hwif.rst | 2 +- src/peakrdl/regblock/field_logic/__init__.py | 1 - src/peakrdl/regblock/module_tmpl.sv | 4 +++- src/peakrdl/regblock/package_tmpl.sv | 4 +++- 7 files changed, 12 insertions(+), 9 deletions(-) diff --git a/docs/architecture.rst b/docs/architecture.rst index 4de1188..daa88f8 100644 --- a/docs/architecture.rst +++ b/docs/architecture.rst @@ -3,7 +3,7 @@ Register Block Architecture The generated register block RTL is organized into several sections. Each section is automatically generated based on the source register model and -is rendered into the output register block SystermVerilog RTL. +is rendered into the output register block SystemVerilog RTL. .. figure:: diagrams/arch.png diff --git a/docs/cpuif/apb3.rst b/docs/cpuif/apb3.rst index 351f674..04999ce 100644 --- a/docs/cpuif/apb3.rst +++ b/docs/cpuif/apb3.rst @@ -10,10 +10,10 @@ The APB3 CPU interface comes in two i/o port flavors: SystemVerilog Interface Class: :class:`peakrdl.regblock.cpuif.apb3.APB3_Cpuif` - Interface Definition: :download:`apb3_intf.sv <../../test/lib/cpuifs/apb3/apb3_intf.sv>` + Interface Definition: :download:`apb3_intf.sv <../../tests/lib/cpuifs/apb3/apb3_intf.sv>` Flattened inputs/outputs - Flattens the interface into descrete input and output ports. + Flattens the interface into discrete input and output ports. Class: :class:`peakrdl.regblock.cpuif.apb3.APB3_Cpuif_flattened` diff --git a/docs/cpuif/axi4lite.rst b/docs/cpuif/axi4lite.rst index 446ae5a..e4070de 100644 --- a/docs/cpuif/axi4lite.rst +++ b/docs/cpuif/axi4lite.rst @@ -12,10 +12,10 @@ The AXI4-Lite CPU interface comes in two i/o port flavors: SystemVerilog Interface Class: :class:`peakrdl.regblock.cpuif.axi4lite.AXI4Lite_Cpuif` - Interface Definition: :download:`apb3_intf.sv <../../test/lib/cpuifs/axi4lite/axi4lite_intf.sv>` + Interface Definition: :download:`axi4lite_intf.sv <../../tests/lib/cpuifs/axi4lite/axi4lite_intf.sv>` Flattened inputs/outputs - Flattens the interface into descrete input and output ports. + Flattens the interface into discrete input and output ports. Class: :class:`peakrdl.regblock.cpuif.axi4lite.AXI4Lite_Cpuif_flattened` diff --git a/docs/hwif.rst b/docs/hwif.rst index c0af714..07cfe03 100644 --- a/docs/hwif.rst +++ b/docs/hwif.rst @@ -8,7 +8,7 @@ using two struct ports: * ``hwif_out`` All field inputs and outputs as well as signals are consolidated into these -struct ports. The presence of each depends on the specific contents of the desgin +struct ports. The presence of each depends on the specific contents of the design being exported. diff --git a/src/peakrdl/regblock/field_logic/__init__.py b/src/peakrdl/regblock/field_logic/__init__.py index 2fbf9be..38da2a4 100644 --- a/src/peakrdl/regblock/field_logic/__init__.py +++ b/src/peakrdl/regblock/field_logic/__init__.py @@ -266,7 +266,6 @@ class FieldLogic: same assignment precedence. """ - # TODO: Add all the other things self.add_sw_conditional(sw_onread.ClearOnRead(self.exp), AssignmentPrecedence.SW_ONREAD) self.add_sw_conditional(sw_onread.SetOnRead(self.exp), AssignmentPrecedence.SW_ONREAD) diff --git a/src/peakrdl/regblock/module_tmpl.sv b/src/peakrdl/regblock/module_tmpl.sv index 5166a74..88a0ba4 100644 --- a/src/peakrdl/regblock/module_tmpl.sv +++ b/src/peakrdl/regblock/module_tmpl.sv @@ -1,4 +1,6 @@ -// TODO: Add a banner +// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator +// https://github.com/SystemRDL/PeakRDL-regblock + module {{module_name}} ( input wire clk, input wire rst, diff --git a/src/peakrdl/regblock/package_tmpl.sv b/src/peakrdl/regblock/package_tmpl.sv index fa9c02d..8a9c43e 100644 --- a/src/peakrdl/regblock/package_tmpl.sv +++ b/src/peakrdl/regblock/package_tmpl.sv @@ -1,4 +1,6 @@ -// TODO: Add a banner +// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator +// https://github.com/SystemRDL/PeakRDL-regblock + package {{hwif.package_name}}; {{hwif.get_package_contents()|indent}} endpackage