bslathi19/PeakRDL-regblock
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This commit is contained in:
Alex Mykyta
2025-11-15 14:47:16 -08:00
parent 7f572e05a4
commit 75a2163f6d
3 changed files with 8 additions and 11 deletions
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4
src/peakrdl_regblock/validate_design.py
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@@ -23,7 +23,6 @@ class DesignValidator(RDLListener):
self.msg = self.top_node.env.msg
self._contains_external_block_stack = [] # type: List[bool]
self.contains_external_block = False
@property
def top_node(self) -> 'AddrmapNode':
@@ -178,9 +177,6 @@ class DesignValidator(RDLListener):
if self._contains_external_block_stack:
# Still in the design. Update stack
self._contains_external_block_stack[-1] |= contains_external_block
else:
# Exiting top addrmap. Resolve final answer
self.contains_external_block = contains_external_block
if contains_external_block:
# Check that addressing follows strict alignment rules to allow