Signals working!

docs/dev_notes/Some Classes

@@ -1,45 +0,0 @@
-
-================================================================================
-Signal wrapper classes
-================================================================================
-Define a signal wrapper class that is easier to use in templates.
-
-Provides the following properties:
-    .is_async
-    .is_activehigh
-    .identifier
-        Returns the Verilog identifier string for this signal
-    .activehigh_identifier
-        Normalizes identifier to active-high logic
-        same as .identifier, but prepends '~' if is_activehigh = False
-    .width
-
-Default reset class instance:
-    Extends the base class
-    Hardcodes as follows:
-        .is_async = True
-        .is_activehigh = True
-        .identifier = "rst"
-        .width = 1
-
-Wrapper classes
-    Wrap around a systemrdl.SignalNode
-
-
-================================================================================
-CPU Interface Class
-================================================================================
-Entry point class for a given CPU interface type (APB, AXI, etc..)
-
-Does the following:
-    - Provide linkage to the logic implementation Jinja template
-    - Interface signal identifier properties
-        Aliases for signal identifiers to allow flat or sv-interface style
-        eg:
-            self.psel --> "s_apb_psel" or "s_apb.psel"
-        if sv interface, use the interface name class prpoerty
-    - Port declaration text property
-        declare as sv interface, or flat port list
-        If flattened, should use signal identifier properties
-        If sv interface, I should breakout the interface & modport name as
-        class properties for easy user-override

docs/dev_notes/Validation Needed

@@ -117,6 +117,7 @@ X incrvalue/decrvalue needs to be the same or narrower than counter itself
 
 ! incrwidth/decrwidth must be between 1 and the width of the counter
 
+
 ================================================================================
 Things that need validation by this exporter
 ================================================================================

docs/dev_notes/template-layers/1.1.hardware-interface

@@ -5,11 +5,37 @@ Summary
 RTL interface that provides access to per-field context signals
 
 Regarding signals:
-    I think RDL-declared signals should actually be part of the hwif input
-    structure.
-    Exceptions:
-        - if the signal instance is at the top-level, it will get promoted to the
-          top level port list for convenience, and therefore omitted from the struct
+    RDL-declared signals are part of the hwif input structure.
+    Only include them if they are referenced by the design (need to scan the
+    full design anyways, so may as well filter out unreferenced ones)
+
+    It is possible to use signals declared in a parent scope.
+    This means that not all signals will be discovered by a hierarchical listener alone
+    Need to scan ALL assigned properties for signal references too.
+        - get signal associated with top node's cpuif_reset helper property, if any
+        - collect all field_resets
+            X check all signal instances in the hier tree
+            - search parents of top node for the first field_reset signal, if any
+                This is WAY less expensive than querying EACH field's resetsignal property
+        X Check all explicitly assigned properties
+            only need to do this for fields
+    Collect all of these into the following:
+        - If inside the hier, add to a list of paths
+        - if outside the hier, add to a dict of path:SignalNode
+    These are all the signals in-use by the design
+
+    Pass list into the hwif generator
+        If the hwif generator encounters a signal during traversal:
+            check if it exists in the signal path list
+
+    out-of-hier signals are inserted outside of the hwif_in as standalone signals.
+    For now, just use their plain inst names. If I need to uniquify them i can add that later.
+    I should at least check against a list of known "dirty words". Seems very likely someone will choose
+    a signal called "rst".
+    Prefix with usersig_ if needed
+
+
+
 
 ================================================================================
 Naming Scheme

docs/props/field.rst

@@ -446,8 +446,8 @@ integer
     |OK|
 
 reference
-    |EX|
+    |OK|
 
 resetsignal
 ^^^^^^^^^^^
-|EX|
+|OK|