Signals working!
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@@ -5,11 +5,37 @@ Summary
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RTL interface that provides access to per-field context signals
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Regarding signals:
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I think RDL-declared signals should actually be part of the hwif input
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structure.
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Exceptions:
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- if the signal instance is at the top-level, it will get promoted to the
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top level port list for convenience, and therefore omitted from the struct
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RDL-declared signals are part of the hwif input structure.
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Only include them if they are referenced by the design (need to scan the
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full design anyways, so may as well filter out unreferenced ones)
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It is possible to use signals declared in a parent scope.
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This means that not all signals will be discovered by a hierarchical listener alone
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Need to scan ALL assigned properties for signal references too.
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- get signal associated with top node's cpuif_reset helper property, if any
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- collect all field_resets
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X check all signal instances in the hier tree
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- search parents of top node for the first field_reset signal, if any
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This is WAY less expensive than querying EACH field's resetsignal property
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X Check all explicitly assigned properties
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only need to do this for fields
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Collect all of these into the following:
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- If inside the hier, add to a list of paths
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- if outside the hier, add to a dict of path:SignalNode
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These are all the signals in-use by the design
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Pass list into the hwif generator
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If the hwif generator encounters a signal during traversal:
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check if it exists in the signal path list
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out-of-hier signals are inserted outside of the hwif_in as standalone signals.
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For now, just use their plain inst names. If I need to uniquify them i can add that later.
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I should at least check against a list of known "dirty words". Seems very likely someone will choose
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a signal called "rst".
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Prefix with usersig_ if needed
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================================================================================
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Naming Scheme
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