Signals working!
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@@ -1,15 +1,15 @@
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from typing import TYPE_CHECKING
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from typing import TYPE_CHECKING, Optional
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from ..utils import get_always_ff_event, clog2
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if TYPE_CHECKING:
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from ..exporter import RegblockExporter
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from ..signals import SignalBase
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from systemrdl import SignalNode
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class CpuifBase:
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template_path = "cpuif/base_tmpl.sv"
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def __init__(self, exp:'RegblockExporter', cpuif_reset:'SignalBase', data_width:int=32, addr_width:int=32):
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def __init__(self, exp:'RegblockExporter', cpuif_reset:Optional['SignalNode'], data_width:int=32, addr_width:int=32):
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self.exp = exp
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self.reset = cpuif_reset
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self.data_width = data_width
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@@ -22,7 +22,8 @@ class CpuifBase:
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def get_implementation(self) -> str:
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context = {
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"cpuif": self,
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"get_always_ff_event": get_always_ff_event,
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"get_always_ff_event": lambda resetsignal : get_always_ff_event(self.exp.dereferencer, resetsignal),
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"get_resetsignal": self.exp.dereferencer.get_resetsignal,
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"clog2": clog2,
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}
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