Lint and typing cleanup

docs/cpuif/customizing.rst

@@ -1,5 +1,5 @@
-Customizing your own CPU interface
-==================================
+Customizing the CPU interface
+=============================
 
 Bring your own SystemVerilog interface
 --------------------------------------
@@ -33,9 +33,11 @@ Rather than rewriting a new CPU interface definition, you can extend and adjust
     class My_AXI4Lite(AXI4Lite_Cpuif):
         @property
         def port_declaration(self) -> str:
+            # Override the port declaration text to use the alternate type name and modport style
             return "axi4_lite_interface.Slave_mp s_axil"
 
         def signal(self, name:str) -> str:
+            # Override the signal names to be lowercase instead
             return "s_axil." + name.lower()
 
 Then use your custom CPUIF during export:

docs/cpuif/internal_protocol.rst

@@ -193,12 +193,13 @@ be the same as a write for a given register block configuration. Typically read
 operations will be more deeply pipelined. This latency asymmetry would create a
 hazard for response collisions.
 
-In order to eliminate this hazard, additional stall signals are provided to delay
-an incoming transfer request if necessary. When asserted, the CPU interface shall
-hold the next pending request until the stall is cleared.
+In order to eliminate this hazard, additional stall signals (``cpuif_req_stall_rd``
+and ``cpuif_req_stall_wr``) are provided to delay the next incoming transfer
+request if necessary. When asserted, the CPU interface shall hold the next pending
+request until the stall is cleared.
 
 For non-pipelined CPU interfaces that only allow one outstanding transaction at a time,
-these can be safely ignored.
+these stall signals can be safely ignored.
 
 In the following example, the regblock is configured such that: