bslathi19/PeakRDL-regblock
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Lint and typing cleanup

Browse Source
This commit is contained in:
Alex Mykyta
2022-02-25 23:05:16 -08:00
parent da3ed05492
commit 7a890b56c5
26 changed files with 852 additions and 94 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
peakrdl/regblock/addr_decode.py
View File

@@ -1,5 +1,4 @@
import re
from typing import TYPE_CHECKING, List, Union
from typing import TYPE_CHECKING, Union, List
from systemrdl.node import AddrmapNode, AddressableNode, RegNode, FieldNode
@@ -60,7 +59,7 @@ class DecodeLogicGenerator(RDLForLoopGenerator):
super().__init__()
# List of address strides for each dimension
self._array_stride_stack = []
self._array_stride_stack = [] # type: List[List[int]]
def enter_AddressableComponent(self, node: 'AddressableNode') -> None:
@@ -80,7 +79,7 @@ class DecodeLogicGenerator(RDLForLoopGenerator):
def _get_address_str(self, node:AddressableNode) -> str:
a = "'h%x" % (node.raw_absolute_address - self.addr_decode.top_node.raw_absolute_address)
a = f"'h{(node.raw_absolute_address - self.addr_decode.top_node.raw_absolute_address):x}"
for i, stride in enumerate(self._array_stride_stack):
a += f" + i{i}*'h{stride:x}"
return a

7
peakrdl/regblock/dereferencer.py
View File

@@ -61,8 +61,7 @@ class Dereferencer:
else:
# No reset value defined!
obj.env.msg.warning(
"Field '%s' is a constant but does not have a known value (missing reset). Assigning it a value of X."
% obj.inst_name,
f"Field '{obj.inst_name}' is a constant but does not have a known value (missing reset). Assigning it a value of X.",
obj.inst.inst_src_ref
)
return "'X"
@@ -79,7 +78,7 @@ class Dereferencer:
else:
raise RuntimeError
raise RuntimeError("Unhandled reference to: %s" % obj)
raise RuntimeError(f"Unhandled reference to: {obj}")
def get_field_propref_value(self, field: FieldNode, prop_name: str) -> str:
@@ -187,7 +186,7 @@ class Dereferencer:
}:
return self.field_logic.get_field_combo_identifier(field, prop_name)
raise RuntimeError("Unhandled reference to: %s->%s" % (field, prop_name))
raise RuntimeError(f"Unhandled reference to: {field}->{prop_name}")
def get_reg_propref_value(self, reg: RegNode, prop_name: str) -> str:

22
peakrdl/regblock/exporter.py
View File

@@ -1,5 +1,5 @@
import os
from typing import Union
from typing import Union, Any, Type
import jinja2 as jj
from systemrdl.node import AddrmapNode, RootNode
@@ -16,10 +16,10 @@ from .utils import get_always_ff_event
from .scan_design import DesignScanner
class RegblockExporter:
def __init__(self, **kwargs) -> None:
def __init__(self, **kwargs: Any) -> None:
# Check for stray kwargs
if kwargs:
raise TypeError("got an unexpected keyword argument '%s'" % list(kwargs.keys())[0])
raise TypeError(f"got an unexpected keyword argument '{list(kwargs.keys())[0]}'")
self.top_node = None # type: AddrmapNode
@@ -45,7 +45,7 @@ class RegblockExporter:
)
def export(self, node: Union[RootNode, AddrmapNode], output_dir:str, **kwargs) -> None:
def export(self, node: Union[RootNode, AddrmapNode], output_dir:str, **kwargs: Any) -> None:
"""
Parameters
----------
@@ -99,18 +99,18 @@ class RegblockExporter:
self.top_node = node
cpuif_cls = kwargs.pop("cpuif_cls", APB3_Cpuif)
module_name = kwargs.pop("module_name", self.top_node.inst_name)
package_name = kwargs.pop("package_name", module_name + "_pkg")
reuse_hwif_typedefs = kwargs.pop("reuse_hwif_typedefs", True)
cpuif_cls = kwargs.pop("cpuif_cls", APB3_Cpuif) # type: Type[CpuifBase]
module_name = kwargs.pop("module_name", self.top_node.inst_name) # type: str
package_name = kwargs.pop("package_name", module_name + "_pkg") # type: str
reuse_hwif_typedefs = kwargs.pop("reuse_hwif_typedefs", True) # type: bool
# Pipelining options
retime_read_fanin = kwargs.pop("retime_read_fanin", False)
retime_read_response = kwargs.pop("retime_read_response", True)
retime_read_fanin = kwargs.pop("retime_read_fanin", False) # type: bool
retime_read_response = kwargs.pop("retime_read_response", True) # type: bool
# Check for stray kwargs
if kwargs:
raise TypeError("got an unexpected keyword argument '%s'" % list(kwargs.keys())[0])
raise TypeError(f"got an unexpected keyword argument '{list(kwargs.keys())[0]}'")
self.min_read_latency = 0
self.min_write_latency = 0

15
peakrdl/regblock/field_logic/generators.py
View File

@@ -1,14 +1,15 @@
from typing import TYPE_CHECKING
from typing import TYPE_CHECKING, List
from collections import OrderedDict
from ..struct_generator import RDLStructGenerator
from ..forloop_generator import RDLForLoopGenerator
from ..utils import get_indexed_path, get_always_ff_event
from ..utils import get_always_ff_event
if TYPE_CHECKING:
from . import FieldLogic
from systemrdl.node import FieldNode, RegNode
from .bases import SVLogic
class CombinationalStructGenerator(RDLStructGenerator):
@@ -23,7 +24,7 @@ class CombinationalStructGenerator(RDLStructGenerator):
return
# collect any extra combo signals that this field requires
extra_combo_signals = OrderedDict()
extra_combo_signals = OrderedDict() # type: OrderedDict[str, SVLogic]
for conditional in self.field_logic.get_conditionals(node):
for signal in conditional.get_extra_combo_signals(node):
if signal.name in extra_combo_signals:
@@ -61,7 +62,7 @@ class CombinationalStructGenerator(RDLStructGenerator):
class FieldStorageStructGenerator(RDLStructGenerator):
def __init__(self, field_logic: 'FieldLogic'):
def __init__(self, field_logic: 'FieldLogic') -> None:
super().__init__()
self.field_logic = field_logic
@@ -79,15 +80,15 @@ class FieldStorageStructGenerator(RDLStructGenerator):
class FieldLogicGenerator(RDLForLoopGenerator):
i_type = "genvar"
def __init__(self, field_logic: 'FieldLogic'):
def __init__(self, field_logic: 'FieldLogic') -> None:
super().__init__()
self.field_logic = field_logic
self.exp = field_logic.exp
self.field_storage_template = self.field_logic.exp.jj_env.get_template(
"field_logic/templates/field_storage.sv"
)
self.intr_fields = []
self.halt_fields = []
self.intr_fields = [] # type: List[FieldNode]
self.halt_fields = [] # type: List[FieldNode]
def enter_Reg(self, node: 'RegNode') -> None:

20
peakrdl/regblock/field_logic/hw_interrupts.py
View File

@@ -1,9 +1,9 @@
from typing import TYPE_CHECKING, List
from .bases import NextStateConditional
from systemrdl.rdltypes import InterruptType
from .bases import NextStateConditional
if TYPE_CHECKING:
from systemrdl.node import FieldNode
@@ -28,7 +28,7 @@ class Sticky(NextStateConditional):
I = self.exp.hwif.get_input_identifier(field)
return [
f"next_c = {I};",
f"load_next_c = '1;",
"load_next_c = '1;",
]
@@ -51,7 +51,7 @@ class Stickybit(NextStateConditional):
R = self.exp.field_logic.get_storage_identifier(field)
return [
f"next_c = {R} | {I};",
f"load_next_c = '1;",
"load_next_c = '1;",
]
class PosedgeStickybit(NextStateConditional):
@@ -77,7 +77,7 @@ class PosedgeStickybit(NextStateConditional):
R = self.exp.field_logic.get_storage_identifier(field)
return [
f"next_c = {R} | (~{Iq} & {I});",
f"load_next_c = '1;",
"load_next_c = '1;",
]
class NegedgeStickybit(NextStateConditional):
@@ -103,7 +103,7 @@ class NegedgeStickybit(NextStateConditional):
R = self.exp.field_logic.get_storage_identifier(field)
return [
f"next_c = {R} | ({Iq} & ~{I});",
f"load_next_c = '1;",
"load_next_c = '1;",
]
class BothedgeStickybit(NextStateConditional):
@@ -129,7 +129,7 @@ class BothedgeStickybit(NextStateConditional):
R = self.exp.field_logic.get_storage_identifier(field)
return [
f"next_c = {R} | ({Iq} ^ {I});",
f"load_next_c = '1;",
"load_next_c = '1;",
]
class PosedgeNonsticky(NextStateConditional):
@@ -152,7 +152,7 @@ class PosedgeNonsticky(NextStateConditional):
Iq = self.exp.field_logic.get_next_q_identifier(field)
return [
f"next_c = ~{Iq} & {I};",
f"load_next_c = '1;",
"load_next_c = '1;",
]
class NegedgeNonsticky(NextStateConditional):
@@ -175,7 +175,7 @@ class NegedgeNonsticky(NextStateConditional):
Iq = self.exp.field_logic.get_next_q_identifier(field)
return [
f"next_c = {Iq} & ~{I};",
f"load_next_c = '1;",
"load_next_c = '1;",
]
class BothedgeNonsticky(NextStateConditional):
@@ -198,5 +198,5 @@ class BothedgeNonsticky(NextStateConditional):
Iq = self.exp.field_logic.get_next_q_identifier(field)
return [
f"next_c = {Iq} ^ {I};",
f"load_next_c = '1;",
"load_next_c = '1;",
]

4
peakrdl/regblock/field_logic/hw_set_clr.py
View File

@@ -35,7 +35,7 @@ class HWSet(NextStateConditional):
return [
f"next_c = {next_val};",
f"load_next_c = '1;",
"load_next_c = '1;",
]
@@ -68,5 +68,5 @@ class HWClear(NextStateConditional):
return [
f"next_c = {next_val};",
f"load_next_c = '1;",
"load_next_c = '1;",
]

2
peakrdl/regblock/field_logic/hw_write.py
View File

@@ -38,7 +38,7 @@ class AlwaysWrite(NextStateConditional):
return [
f"next_c = {next_val};",
f"load_next_c = '1;",
"load_next_c = '1;",
]
class WEWrite(AlwaysWrite):

8
peakrdl/regblock/field_logic/sw_onread.py
View File

@@ -23,8 +23,8 @@ class ClearOnRead(_OnRead):
def get_assignments(self, field: 'FieldNode') -> List[str]:
return [
f"next_c = '0;",
f"load_next_c = '1;",
"next_c = '0;",
"load_next_c = '1;",
]
@@ -34,6 +34,6 @@ class SetOnRead(_OnRead):
def get_assignments(self, field: 'FieldNode') -> List[str]:
return [
f"next_c = '1;",
f"load_next_c = '1;",
"next_c = '1;",
"load_next_c = '1;",
]

22
peakrdl/regblock/field_logic/sw_onwrite.py
View File

@@ -41,7 +41,7 @@ class WriteOneSet(_OnWrite):
R = self.exp.field_logic.get_storage_identifier(field)
return [
f"next_c = {R} | {self._wr_data(field)};",
f"load_next_c = '1;",
"load_next_c = '1;",
]
class WriteOneClear(_OnWrite):
@@ -52,7 +52,7 @@ class WriteOneClear(_OnWrite):
R = self.exp.field_logic.get_storage_identifier(field)
return [
f"next_c = {R} & ~{self._wr_data(field)};",
f"load_next_c = '1;",
"load_next_c = '1;",
]
class WriteOneToggle(_OnWrite):
@@ -63,7 +63,7 @@ class WriteOneToggle(_OnWrite):
R = self.exp.field_logic.get_storage_identifier(field)
return [
f"next_c = {R} ^ {self._wr_data(field)};",
f"load_next_c = '1;",
"load_next_c = '1;",
]
class WriteZeroSet(_OnWrite):
@@ -74,7 +74,7 @@ class WriteZeroSet(_OnWrite):
R = self.exp.field_logic.get_storage_identifier(field)
return [
f"next_c = {R} | ~{self._wr_data(field)};",
f"load_next_c = '1;",
"load_next_c = '1;",
]
class WriteZeroClear(_OnWrite):
@@ -85,7 +85,7 @@ class WriteZeroClear(_OnWrite):
R = self.exp.field_logic.get_storage_identifier(field)
return [
f"next_c = {R} & {self._wr_data(field)};",
f"load_next_c = '1;",
"load_next_c = '1;",
]
class WriteZeroToggle(_OnWrite):
@@ -96,7 +96,7 @@ class WriteZeroToggle(_OnWrite):
R = self.exp.field_logic.get_storage_identifier(field)
return [
f"next_c = {R} ^ ~{self._wr_data(field)};",
f"load_next_c = '1;",
"load_next_c = '1;",
]
class WriteClear(_OnWrite):
@@ -105,8 +105,8 @@ class WriteClear(_OnWrite):
def get_assignments(self, field: 'FieldNode') -> List[str]:
return [
f"next_c = '0;",
f"load_next_c = '1;",
"next_c = '0;",
"load_next_c = '1;",
]
class WriteSet(_OnWrite):
@@ -115,8 +115,8 @@ class WriteSet(_OnWrite):
def get_assignments(self, field: 'FieldNode') -> List[str]:
return [
f"next_c = '1;",
f"load_next_c = '1;",
"next_c = '1;",
"load_next_c = '1;",
]
class Write(_OnWrite):
@@ -126,5 +126,5 @@ class Write(_OnWrite):
def get_assignments(self, field: 'FieldNode') -> List[str]:
return [
f"next_c = {self._wr_data(field)};",
f"load_next_c = '1;",
"load_next_c = '1;",
]

4
peakrdl/regblock/field_logic/sw_singlepulse.py
View File

@@ -17,6 +17,6 @@ class Singlepulse(NextStateConditional):
def get_assignments(self, field: 'FieldNode') -> List[str]:
return [
f"next_c = '0;",
f"load_next_c = '1;",
"next_c = '0;",
"load_next_c = '1;",
]

8
peakrdl/regblock/forloop_generator.py
View File

@@ -1,4 +1,4 @@
from typing import TYPE_CHECKING, Optional, List
from typing import TYPE_CHECKING, Optional, List, Union
import textwrap
from systemrdl.walker import RDLListener, RDLWalker
@@ -9,7 +9,7 @@ if TYPE_CHECKING:
class Body:
def __init__(self) -> None:
self.children = []
self.children = [] # type: List[Union[str, Body]]
def __str__(self) -> str:
s = '\n'.join((str(x) for x in self.children))
@@ -37,7 +37,7 @@ class ForLoopGenerator:
def __init__(self) -> None:
self._loop_level = 0
self._stack = []
self._stack = [] # type: List[Body]
@property
def current_loop(self) -> Body:
@@ -60,7 +60,7 @@ class ForLoopGenerator:
self.current_loop.children.append(b)
self._loop_level -= 1
def start(self):
def start(self) -> None:
assert not self._stack
b = Body()
self._stack.append(b)

8
peakrdl/regblock/hwif/__init__.py
View File

@@ -27,8 +27,8 @@ class Hwif:
self.exp = exp
self.package_name = package_name
self.has_input_struct = None
self.has_output_struct = None
self.has_input_struct = False
self.has_output_struct = False
self.in_hier_signal_paths = in_hier_signal_paths
self.out_of_hier_signals = out_of_hier_signals
@@ -147,7 +147,7 @@ class Hwif:
elif isinstance(obj, PropertyReference):
return self.get_implied_prop_input_identifier(obj.node, obj.name)
raise RuntimeError("Unhandled reference to: %s", obj)
raise RuntimeError(f"Unhandled reference to: {obj}")
def get_implied_prop_input_identifier(self, field: FieldNode, prop: str) -> str:
@@ -179,7 +179,7 @@ class Hwif:
assert obj.node.get_property(obj.name)
return self.get_implied_prop_output_identifier(obj.node, obj.name)
raise RuntimeError("Unhandled reference to: %s", obj)
raise RuntimeError(f"Unhandled reference to: {obj}")
def get_implied_prop_output_identifier(self, node: Union[FieldNode, RegNode], prop: str) -> str:

6
peakrdl/regblock/hwif/generators.py
View File

@@ -1,13 +1,15 @@
from typing import TYPE_CHECKING
from ..struct_generator import RDLFlatStructGenerator
from systemrdl.node import FieldNode
from ..struct_generator import RDLFlatStructGenerator
if TYPE_CHECKING:
from systemrdl.node import Node, SignalNode, RegNode
from . import Hwif
class InputStructGenerator_Hier(RDLFlatStructGenerator):
def __init__(self, hwif: 'Hwif'):
def __init__(self, hwif: 'Hwif') -> None:
super().__init__()
self.hwif = hwif
self.top_node = hwif.top_node

8
peakrdl/regblock/readback/generators.py
View File

@@ -1,4 +1,4 @@
from typing import TYPE_CHECKING
from typing import TYPE_CHECKING, List
from ..forloop_generator import RDLForLoopGenerator, LoopBody
@@ -30,8 +30,8 @@ class ReadbackAssignmentGenerator(RDLForLoopGenerator):
# array. The array width is equal to the CPUIF bus width. Each entry in
# the array represents an aligned read access.
self.current_offset = 0
self.start_offset_stack = []
self.dim_stack = []
self.start_offset_stack = [] # type: List[int]
self.dim_stack = [] # type: List[int]
@property
def current_offset_str(self) -> str:
@@ -99,7 +99,7 @@ class ReadbackAssignmentGenerator(RDLForLoopGenerator):
# Number of registers enclosed in this loop
n_regs = self.current_offset - start_offset
self.current_loop.n_regs = n_regs
self.current_loop.n_regs = n_regs # type: ignore
super().pop_loop()

12
peakrdl/regblock/scan_design.py
View File

@@ -1,4 +1,4 @@
from typing import TYPE_CHECKING
from typing import TYPE_CHECKING, Set
from collections import OrderedDict
from systemrdl.walker import RDLListener, RDLWalker
@@ -16,16 +16,16 @@ class DesignScanner(RDLListener):
Also collects any information that is required prior to the start of the export process.
"""
def __init__(self, exp:'RegblockExporter'):
def __init__(self, exp:'RegblockExporter') -> None:
self.exp = exp
self.cpuif_data_width = 0
self.msg = exp.top_node.env.msg
# Collections of signals that were actually referenced by the design
self.in_hier_signal_paths = set()
self.out_of_hier_signals = OrderedDict()
self.in_hier_signal_paths = set() # type: Set[str]
self.out_of_hier_signals = OrderedDict() # type: OrderedDict[str, SignalNode]
def _get_out_of_hier_field_reset(self):
def _get_out_of_hier_field_reset(self) -> None:
current_node = self.exp.top_node.parent
while current_node is not None:
for signal in current_node.signals():
@@ -35,7 +35,7 @@ class DesignScanner(RDLListener):
return
current_node = current_node.parent
def do_scan(self):
def do_scan(self) -> None:
# Collect cpuif reset, if any.
cpuif_reset = self.exp.top_node.cpuif_reset
if cpuif_reset is not None:

18
peakrdl/regblock/struct_generator.py
View File

@@ -11,8 +11,8 @@ if TYPE_CHECKING:
class _StructBase:
def __init__(self):
self.children = [] # type: Union[str, _StructBase]
def __init__(self) -> None:
self.children = [] # type: List[Union[str, _StructBase]]
def __str__(self) -> str:
s = '\n'.join((str(x) for x in self.children))
@@ -65,8 +65,8 @@ class _TypedefStruct(_StructBase):
class StructGenerator:
def __init__(self):
self._struct_stack = []
def __init__(self) -> None:
self._struct_stack = [] # type: List[_StructBase]
@property
def current_struct(self) -> _StructBase:
@@ -99,7 +99,7 @@ class StructGenerator:
self.current_struct.children.append(s)
def start(self, type_name: str):
def start(self, type_name: str) -> None:
assert not self._struct_stack
s = _TypedefStruct(type_name)
self._struct_stack.append(s)
@@ -155,16 +155,17 @@ class RDLStructGenerator(StructGenerator, RDLListener):
class FlatStructGenerator(StructGenerator):
def __init__(self):
def __init__(self) -> None:
super().__init__()
self.typedefs = OrderedDict()
self.typedefs = OrderedDict() # type: OrderedDict[str, _TypedefStruct]
def push_struct(self, type_name: str, inst_name: str, array_dimensions: Optional[List[int]] = None) -> None:
def push_struct(self, type_name: str, inst_name: str, array_dimensions: Optional[List[int]] = None) -> None: # type: ignore # pylint: disable=arguments-differ
s = _TypedefStruct(type_name, inst_name, array_dimensions)
self._struct_stack.append(s)
def pop_struct(self) -> None:
s = self._struct_stack.pop()
assert isinstance(s, _TypedefStruct)
if s.children:
# struct is not empty. Attach it to the parent
@@ -176,6 +177,7 @@ class FlatStructGenerator(StructGenerator):
def finish(self) -> Optional[str]:
s = self._struct_stack.pop()
assert isinstance(s, _TypedefStruct)
assert not self._struct_stack
# no children, no struct.

6
peakrdl/regblock/utils.py
View File

@@ -1,5 +1,5 @@
import re
from typing import TYPE_CHECKING
from typing import TYPE_CHECKING, Match
if TYPE_CHECKING:
from systemrdl.node import Node, SignalNode
@@ -13,9 +13,9 @@ def get_indexed_path(top_node: 'Node', target_node: 'Node') -> str:
path = target_node.get_rel_path(top_node, empty_array_suffix="[!]")
# replace unknown indexes with incrementing iterators i0, i1, ...
class repl:
def __init__(self):
def __init__(self) -> None:
self.i = 0
def __call__(self, match):
def __call__(self, match: Match) -> str:
s = f'i{self.i}'
self.i += 1
return s