Lint and typing cleanup
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@@ -1,14 +1,15 @@
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from typing import TYPE_CHECKING
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from typing import TYPE_CHECKING, List
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from collections import OrderedDict
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from ..struct_generator import RDLStructGenerator
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from ..forloop_generator import RDLForLoopGenerator
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from ..utils import get_indexed_path, get_always_ff_event
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from ..utils import get_always_ff_event
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if TYPE_CHECKING:
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from . import FieldLogic
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from systemrdl.node import FieldNode, RegNode
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from .bases import SVLogic
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class CombinationalStructGenerator(RDLStructGenerator):
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@@ -23,7 +24,7 @@ class CombinationalStructGenerator(RDLStructGenerator):
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return
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# collect any extra combo signals that this field requires
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extra_combo_signals = OrderedDict()
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extra_combo_signals = OrderedDict() # type: OrderedDict[str, SVLogic]
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for conditional in self.field_logic.get_conditionals(node):
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for signal in conditional.get_extra_combo_signals(node):
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if signal.name in extra_combo_signals:
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@@ -61,7 +62,7 @@ class CombinationalStructGenerator(RDLStructGenerator):
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class FieldStorageStructGenerator(RDLStructGenerator):
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def __init__(self, field_logic: 'FieldLogic'):
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def __init__(self, field_logic: 'FieldLogic') -> None:
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super().__init__()
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self.field_logic = field_logic
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@@ -79,15 +80,15 @@ class FieldStorageStructGenerator(RDLStructGenerator):
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class FieldLogicGenerator(RDLForLoopGenerator):
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i_type = "genvar"
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def __init__(self, field_logic: 'FieldLogic'):
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def __init__(self, field_logic: 'FieldLogic') -> None:
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super().__init__()
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self.field_logic = field_logic
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self.exp = field_logic.exp
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self.field_storage_template = self.field_logic.exp.jj_env.get_template(
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"field_logic/templates/field_storage.sv"
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)
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self.intr_fields = []
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self.halt_fields = []
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self.intr_fields = [] # type: List[FieldNode]
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self.halt_fields = [] # type: List[FieldNode]
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def enter_Reg(self, node: 'RegNode') -> None:
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