From 7fcd0e599b3e0aed963c9796a302d10a5a4b0766 Mon Sep 17 00:00:00 2001 From: Alex Mykyta Date: Fri, 17 Feb 2023 23:14:50 -0800 Subject: [PATCH] Update peakrdl plugin to extend from base class --- src/peakrdl_regblock/__peakrdl__.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/peakrdl_regblock/__peakrdl__.py b/src/peakrdl_regblock/__peakrdl__.py index 2ce1fa4..7cfbee6 100644 --- a/src/peakrdl_regblock/__peakrdl__.py +++ b/src/peakrdl_regblock/__peakrdl__.py @@ -1,5 +1,7 @@ from typing import TYPE_CHECKING +from peakrdl.plugins.exporter import ExporterSubcommandPlugin #pylint: disable=import-error + from .exporter import RegblockExporter from .cpuif import apb3, apb4, axi4lite, passthrough, CpuifBase from .udps import ALL_UDPS @@ -31,7 +33,7 @@ for ep, dist in entry_points.get_entry_points("peakrdl_regblock.cpuif"): CPUIF_DICT[name] = cpuif -class Exporter: +class Exporter(ExporterSubcommandPlugin): short_desc = "Generate a SystemVerilog control/status register (CSR) block" udp_definitions = ALL_UDPS