Fix synthesizability of fields with msb0 ordering

2022-10-17 22:09:39 -07:00
parent e07e7d26b2
commit 808067fac9
7 changed files with 39 additions and 11 deletions
--- a/src/peakrdl_regblock/exporter.py
+++ b/src/peakrdl_regblock/exporter.py
@@ -152,6 +152,7 @@ class RegblockExporter:
        context = {
            "module_name": module_name,
            "user_out_of_hier_signals": scanner.out_of_hier_signals.values(),
+            "has_writable_msb0_fields": scanner.has_writable_msb0_fields,
            "cpuif": self.cpuif,
            "hwif": self.hwif,
            "get_resetsignal": self.dereferencer.get_resetsignal,