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Fix synthesizability of fields with msb0 ordering

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This commit is contained in:
Alex Mykyta
2022-10-17 22:09:39 -07:00
parent e07e7d26b2
commit 808067fac9
7 changed files with 39 additions and 11 deletions
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12
src/peakrdl_regblock/field_logic/sw_onwrite.py
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@@ -40,6 +40,14 @@ class _OnWrite(NextStateConditional):
high = max(min(high, accesswidth), 0)
low = max(min(low, accesswidth), 0)
if field.msb < field.lsb:
# slice is for an msb0 field.
# mirror it
bus_width = self.exp.cpuif.data_width
low = bus_width - 1 - low
high = bus_width - 1 - high
low, high = high, low
return f"[{high}:{low}]"
def _wr_data(self, field: 'FieldNode', subword_idx: int=0) -> str:
@@ -47,7 +55,7 @@ class _OnWrite(NextStateConditional):
if field.msb < field.lsb:
# Field gets bitswapped since it is in [low:high] orientation
value = f"{{<<{{decoded_wr_data{bslice}}}}}"
value = f"decoded_wr_data_bswap{bslice}"
else:
value = f"decoded_wr_data{bslice}"
return value
@@ -57,7 +65,7 @@ class _OnWrite(NextStateConditional):
if field.msb < field.lsb:
# Field gets bitswapped since it is in [low:high] orientation
value = f"{{<<{{decoded_wr_biten{bslice}}}}}"
value = f"decoded_wr_biten_bswap{bslice}"
else:
value = f"decoded_wr_biten{bslice}"
return value