Fix synthesizability of fields with msb0 ordering

tests/lib/simulators/xilinx.py

@@ -7,8 +7,10 @@ from . import Simulator
 class Xilinx(Simulator):
     """
     Don't bother using the Xilinx simulator... Its buggy and extraordinarily slow.
-    As observed in v2021.1, clocking block assignments do not seem to actually simulate
-    correctly - assignment statements get ignored or the values get mangled.
+    As observed in v2021.1:
+        - clocking block assignments do not seem to actually simulate correctly.
+          assignment statements get ignored or the values get mangled.
+        - Streaming operators have all sorts of limitations.
 
     Keeping this here in case someday it works better...
     """
@@ -16,6 +18,7 @@ class Xilinx(Simulator):
         cmd = [
             "xvlog", "--sv",
             "--include", os.path.join(os.path.dirname(__file__), ".."),
+            "--define", "XSIM",
         ]
         cmd.extend(self.tb_files)
         subprocess.run(cmd, check=True)

tests/test_structural_sw_rw/tb_template.sv

@@ -71,10 +71,13 @@
     cpuif.assert_read('h3000, 'h4DEAB000);
 
     // rw_reg_lsb0
-    cpuif.assert_read('h3004, 0);
-    cpuif.write('h3004, 'h4DEAB000);
-    @cb;
-    assert({<<{cb.hwif_out.rw_reg_lsb0.f1.value}} == 8'hAB);
-    assert({<<{cb.hwif_out.rw_reg_lsb0.f2.value}} == 11'h4DE);
-    cpuif.assert_read('h3004, 'h4DEAB000);
+    `ifndef XSIM
+        // Xilinx simulator has poor support for streaming operators. Skip
+        cpuif.assert_read('h3004, 0);
+        cpuif.write('h3004, 'h4DEAB000);
+        @cb;
+        assert({<<{cb.hwif_out.rw_reg_lsb0.f1.value}} == 8'hAB);
+        assert({<<{cb.hwif_out.rw_reg_lsb0.f2.value}} == 11'h4DE);
+        cpuif.assert_read('h3004, 'h4DEAB000);
+    `endif
 {% endblock %}