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Fix synthesizability of fields with msb0 ordering

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This commit is contained in:
Alex Mykyta
2022-10-17 22:09:39 -07:00
parent e07e7d26b2
commit 808067fac9
7 changed files with 39 additions and 11 deletions
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15
tests/test_structural_sw_rw/tb_template.sv
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@@ -71,10 +71,13 @@
cpuif.assert_read('h3000, 'h4DEAB000);
// rw_reg_lsb0
cpuif.assert_read('h3004, 0);
cpuif.write('h3004, 'h4DEAB000);
@cb;
assert({<<{cb.hwif_out.rw_reg_lsb0.f1.value}} == 8'hAB);
assert({<<{cb.hwif_out.rw_reg_lsb0.f2.value}} == 11'h4DE);
cpuif.assert_read('h3004, 'h4DEAB000);
`ifndef XSIM
// Xilinx simulator has poor support for streaming operators. Skip
cpuif.assert_read('h3004, 0);
cpuif.write('h3004, 'h4DEAB000);
@cb;
assert({<<{cb.hwif_out.rw_reg_lsb0.f1.value}} == 8'hAB);
assert({<<{cb.hwif_out.rw_reg_lsb0.f2.value}} == 11'h4DE);
cpuif.assert_read('h3004, 'h4DEAB000);
`endif
{% endblock %}