bslathi19/PeakRDL-regblock
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Fix incorrect address width calculation for external blocks. #116

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Alex Mykyta
2024-12-19 19:40:57 -08:00
parent 5f9d7308c2
commit 80a46a082b
1 changed files with 1 additions and 1 deletions
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src/peakrdl_regblock/field_logic/generators.py
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@@ -362,7 +362,7 @@ class FieldLogicGenerator(RDLForLoopGenerator):
def assign_external_block_outputs(self, node: 'AddressableNode') -> None: def assign_external_block_outputs(self, node: 'AddressableNode') -> None:
prefix = "hwif_out." + get_indexed_path(self.exp.ds.top_node, node) prefix = "hwif_out." + get_indexed_path(self.exp.ds.top_node, node)
strb = self.exp.dereferencer.get_external_block_access_strobe(node) strb = self.exp.dereferencer.get_external_block_access_strobe(node)
addr_width = node.size.bit_length() addr_width = (node.size - 1).bit_length()
retime = False retime = False
if isinstance(node, RegfileNode): if isinstance(node, RegfileNode):