bslathi19/PeakRDL-regblock
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fix wavedrom json commas

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This commit is contained in:
Alex Mykyta
2022-02-21 22:44:07 -08:00
parent 98ab38ae4d
commit 88f90e4f85
1 changed files with 6 additions and 7 deletions
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13
docs/cpuif/internal_protocol.rst
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@@ -100,7 +100,7 @@ Both are valid and CPU interface logic shall be designed to anticipate either.
{"name": "cpuif_addr", "wave": "x2x..", "data": ["A"]}, {"name": "cpuif_addr", "wave": "x2x..", "data": ["A"]},
{}, {},
{"name": "cpuif_*_ack", "wave": "010.."}, {"name": "cpuif_*_ack", "wave": "010.."},
{"name": "cpuif_*_err", "wave": "x2x.."}, {"name": "cpuif_*_err", "wave": "x2x.."}
], ],
"foot": { "foot": {
"text": "Zero-latency transfer" "text": "Zero-latency transfer"
@@ -117,7 +117,7 @@ Both are valid and CPU interface logic shall be designed to anticipate either.
{"name": "cpuif_addr", "wave": "x2x|...", "data": ["A"]}, {"name": "cpuif_addr", "wave": "x2x|...", "data": ["A"]},
{}, {},
{"name": "cpuif_*_ack", "wave": "0..|10."}, {"name": "cpuif_*_ack", "wave": "0..|10."},
{"name": "cpuif_*_err", "wave": "x..|2x."}, {"name": "cpuif_*_err", "wave": "x..|2x."}
], ],
"foot": { "foot": {
"text": "Transfer with non-zero latency" "text": "Transfer with non-zero latency"
@@ -142,7 +142,7 @@ For brevity, only showing non-zero latency transfers.
{}, {},
{"name": "cpuif_rd_ack", "wave": "0..|10."}, {"name": "cpuif_rd_ack", "wave": "0..|10."},
{"name": "cpuif_rd_err", "wave": "x..|0x."}, {"name": "cpuif_rd_err", "wave": "x..|0x."},
{"name": "cpuif_rd_data", "wave": "x..|5x.", "data": ["D"]}, {"name": "cpuif_rd_data", "wave": "x..|5x.", "data": ["D"]}
], ],
"foot": { "foot": {
"text": "Read Transaction" "text": "Read Transaction"
@@ -161,7 +161,7 @@ For brevity, only showing non-zero latency transfers.
{"name": "cpuif_wr_data", "wave": "x5x|...", "data": ["D"]}, {"name": "cpuif_wr_data", "wave": "x5x|...", "data": ["D"]},
{}, {},
{"name": "cpuif_wr_ack", "wave": "0..|10."}, {"name": "cpuif_wr_ack", "wave": "0..|10."},
{"name": "cpuif_wr_err", "wave": "x..|0x."}, {"name": "cpuif_wr_err", "wave": "x..|0x."}
], ],
"foot": { "foot": {
"text": "Write Transaction" "text": "Write Transaction"
@@ -184,7 +184,7 @@ If the CPU interface supports it, read and write operations can be pipelined.
{}, {},
{"name": "cpuif_rd_ack", "wave": "0.1..0."}, {"name": "cpuif_rd_ack", "wave": "0.1..0."},
{"name": "cpuif_rd_err", "wave": "x.0..x."}, {"name": "cpuif_rd_err", "wave": "x.0..x."},
{"name": "cpuif_rd_data", "wave": "x.555x.", "data": ["D1", "D2", "D3"]}, {"name": "cpuif_rd_data", "wave": "x.555x.", "data": ["D1", "D2", "D3"]}
] ]
} }
@@ -216,8 +216,7 @@ In the following example, the regblock is configured such that:
{"name": "cpuif_req_stall_wr", "wave": "0...1.0."}, {"name": "cpuif_req_stall_wr", "wave": "0...1.0."},
{}, {},
{"name": "cpuif_rd_ack", "wave": "0...220.", "data": ["R1", "R2"]}, {"name": "cpuif_rd_ack", "wave": "0...220.", "data": ["R1", "R2"]},
{"name": "cpuif_wr_ack", "wave": "0220..20", "data": ["W1", "W2", "W3"]}, {"name": "cpuif_wr_ack", "wave": "0220..20", "data": ["W1", "W2", "W3"]}
] ]
} }