From 8b82f9f725e6bbc7de67a259c67d7f87d77836da Mon Sep 17 00:00:00 2001
From: Alex Mykyta <amykyta3@users.noreply.github.com>
Date: Fri, 29 Jul 2022 23:32:15 -0700
Subject: [PATCH] Add pre-production warning

---
 docs/index.rst | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/docs/index.rst b/docs/index.rst
index dabb127..c89031f 100644
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -12,6 +12,10 @@ your hardware design.
 * Broad support for SystemRDL 2.0 features
 * Fully synthesizable SystemVerilog. Tested on Xilinx/AMD's Vivado & Intel Quartus
 
+.. warning::
+
+    The PeakRDL-regblock SV generator is still in pre-production (v0.x version numbers).
+    During this time, I may decide to refactor things which could break compatibility.
 
 
 Installing