Switch to use regular non-namespaced package

2022-06-09 20:24:53 -07:00
parent 693040d145
commit 8d13a9d7fe
52 changed files with 26 additions and 27 deletions
--- a/src/peakrdl_regblock/about.py
+++ b/src/peakrdl_regblock/about.py
--- a/src/peakrdl_regblock/init.py
+++ b/src/peakrdl_regblock/init.py
--- a/src/peakrdl_regblock/addr_decode.py
+++ b/src/peakrdl_regblock/addr_decode.py
--- a/src/peakrdl_regblock/cpuif/init.py
+++ b/src/peakrdl_regblock/cpuif/init.py
--- a/src/peakrdl_regblock/cpuif/apb3/init.py
+++ b/src/peakrdl_regblock/cpuif/apb3/init.py
--- a/src/peakrdl_regblock/cpuif/apb3/apb3_tmpl.sv
+++ b/src/peakrdl_regblock/cpuif/apb3/apb3_tmpl.sv
--- a/src/peakrdl_regblock/cpuif/axi4lite/init.py
+++ b/src/peakrdl_regblock/cpuif/axi4lite/init.py
--- a/src/peakrdl_regblock/cpuif/axi4lite/axi4lite_tmpl.sv
+++ b/src/peakrdl_regblock/cpuif/axi4lite/axi4lite_tmpl.sv
--- a/src/peakrdl_regblock/cpuif/base.py
+++ b/src/peakrdl_regblock/cpuif/base.py
--- a/src/peakrdl_regblock/cpuif/passthrough/init.py
+++ b/src/peakrdl_regblock/cpuif/passthrough/init.py
--- a/src/peakrdl_regblock/cpuif/passthrough/passthrough_tmpl.sv
+++ b/src/peakrdl_regblock/cpuif/passthrough/passthrough_tmpl.sv
--- a/src/peakrdl_regblock/dereferencer.py
+++ b/src/peakrdl_regblock/dereferencer.py
--- a/src/peakrdl_regblock/exporter.py
+++ b/src/peakrdl_regblock/exporter.py
@@ -54,7 +54,7 @@ class RegblockExporter:
        output_dir: str
            Path to the output directory where generated SystemVerilog will be written.
            Output includes two files: a module definition and package definition.
-        cpuif_cls: :class:`peakrdl.regblock.cpuif.CpuifBase`
+        cpuif_cls: :class:`peakrdl_regblock.cpuif.CpuifBase`
            Specify the class type that implements the CPU interface of your choice.
            Defaults to AMBA APB3.
        module_name: str
--- a/src/peakrdl_regblock/field_logic/init.py
+++ b/src/peakrdl_regblock/field_logic/init.py
--- a/src/peakrdl_regblock/field_logic/bases.py
+++ b/src/peakrdl_regblock/field_logic/bases.py
--- a/src/peakrdl_regblock/field_logic/generators.py
+++ b/src/peakrdl_regblock/field_logic/generators.py
--- a/src/peakrdl_regblock/field_logic/hw_interrupts.py
+++ b/src/peakrdl_regblock/field_logic/hw_interrupts.py
--- a/src/peakrdl_regblock/field_logic/hw_set_clr.py
+++ b/src/peakrdl_regblock/field_logic/hw_set_clr.py
--- a/src/peakrdl_regblock/field_logic/hw_write.py
+++ b/src/peakrdl_regblock/field_logic/hw_write.py
--- a/src/peakrdl_regblock/field_logic/sw_onread.py
+++ b/src/peakrdl_regblock/field_logic/sw_onread.py
--- a/src/peakrdl_regblock/field_logic/sw_onwrite.py
+++ b/src/peakrdl_regblock/field_logic/sw_onwrite.py
--- a/src/peakrdl_regblock/field_logic/sw_singlepulse.py
+++ b/src/peakrdl_regblock/field_logic/sw_singlepulse.py
--- a/src/peakrdl_regblock/field_logic/templates/counter_macros.sv
+++ b/src/peakrdl_regblock/field_logic/templates/counter_macros.sv
--- a/src/peakrdl_regblock/field_logic/templates/field_storage.sv
+++ b/src/peakrdl_regblock/field_logic/templates/field_storage.sv
--- a/src/peakrdl_regblock/forloop_generator.py
+++ b/src/peakrdl_regblock/forloop_generator.py
--- a/src/peakrdl_regblock/hwif/init.py
+++ b/src/peakrdl_regblock/hwif/init.py
--- a/src/peakrdl_regblock/hwif/generators.py
+++ b/src/peakrdl_regblock/hwif/generators.py
--- a/src/peakrdl_regblock/module_tmpl.sv
+++ b/src/peakrdl_regblock/module_tmpl.sv
--- a/src/peakrdl_regblock/package_tmpl.sv
+++ b/src/peakrdl_regblock/package_tmpl.sv
--- a/src/peakrdl_regblock/readback/init.py
+++ b/src/peakrdl_regblock/readback/init.py
--- a/src/peakrdl_regblock/readback/generators.py
+++ b/src/peakrdl_regblock/readback/generators.py
--- a/src/peakrdl_regblock/readback/templates/readback.sv
+++ b/src/peakrdl_regblock/readback/templates/readback.sv
--- a/src/peakrdl_regblock/scan_design.py
+++ b/src/peakrdl_regblock/scan_design.py
--- a/src/peakrdl_regblock/struct_generator.py
+++ b/src/peakrdl_regblock/struct_generator.py
--- a/src/peakrdl_regblock/utils.py
+++ b/src/peakrdl_regblock/utils.py