Revise implementation of 'next' property

This commit is contained in:
Alex Mykyta
2021-12-20 12:21:51 -08:00
parent 769907404a
commit 8ed45ed632
8 changed files with 85 additions and 40 deletions

View File

@@ -15,13 +15,13 @@
cpuif.assert_read('h0, 11);
assert(cb.hwif_out.r1.f.value == 11);
cb.hwif_in.r1.f.value <= 9;
cb.hwif_in.r1.f.next <= 9;
cpuif.assert_read('h0, 11);
assert(cb.hwif_out.r1.f.value == 11);
cb.hwif_in.r1.f.value <= 12;
cb.hwif_in.r1.f.next <= 12;
cb.hwif_in.r1.f.we <= 1;
@cb;
cb.hwif_in.r1.f.value <= 0;
cb.hwif_in.r1.f.next <= 0;
cb.hwif_in.r1.f.we <= 0;
cpuif.assert_read('h0, 12);
assert(cb.hwif_out.r1.f.value == 12);
@@ -42,12 +42,12 @@
cpuif.write('h2, 31);
cpuif.assert_read('h2, 31);
cb.hwif_in.r3.f.value <= 29;
cb.hwif_in.r3.f.next <= 29;
cpuif.assert_read('h2, 31);
cb.hwif_in.r3.f.value <= 32;
cb.hwif_in.r3.f.next <= 32;
cb.hwif_in.r3.f.wel <= 0;
@cb;
cb.hwif_in.r3.f.value <= 0;
cb.hwif_in.r3.f.next <= 0;
cb.hwif_in.r3.f.wel <= 1;
cpuif.assert_read('h2, 32);
@@ -66,13 +66,13 @@
cpuif.assert_read('h4, 50);
assert(cb.hwif_out.r5.f.value == 50);
cb.hwif_in.r5.f.value <= 9;
cb.hwif_in.r5.f.next <= 9;
cpuif.assert_read('h4, 50);
assert(cb.hwif_out.r5.f.value == 50);
cb.hwif_in.r5.f.value <= 52;
cb.hwif_in.r5.f.next <= 52;
cb.hwif_in.r5.f.we <= 1;
@cb;
cb.hwif_in.r5.f.value <= 0;
cb.hwif_in.r5.f.next <= 0;
cb.hwif_in.r5.f.we <= 0;
cpuif.assert_read('h4, 52);
assert(cb.hwif_out.r5.f.value == 52);
@@ -88,7 +88,7 @@
// r7 - sw=r; hw=w; // Wire/Bus - hardware assigns value
cpuif.assert_read('h6, 0);
cb.hwif_in.r7.f.value <= 70;
cb.hwif_in.r7.f.next <= 70;
cpuif.assert_read('h6, 70);
cpuif.write('h6, 71);
cpuif.assert_read('h6, 70);
@@ -108,13 +108,13 @@
cpuif.assert_read('h8, 0);
assert(cb.hwif_out.r9.f.value == 91);
cb.hwif_in.r9.f.value <= 89;
cb.hwif_in.r9.f.next <= 89;
cpuif.assert_read('h8, 0);
assert(cb.hwif_out.r9.f.value == 91);
cb.hwif_in.r9.f.value <= 92;
cb.hwif_in.r9.f.next <= 92;
cb.hwif_in.r9.f.we <= 1;
@cb;
cb.hwif_in.r9.f.value <= 0;
cb.hwif_in.r9.f.next <= 0;
cb.hwif_in.r9.f.we <= 0;
cpuif.assert_read('h8, 0);
assert(cb.hwif_out.r9.f.value == 92);

View File

@@ -60,4 +60,14 @@ addrmap top {
} f[7:0] = 0x44;
} r4;
r4.f->wel = hw_ctrl.hw_wel;
reg {
signal {} f_next_value[8];
signal {} f_we;
field {
sw=rw; hw=w;
next = f_next_value;
we = f_we;
} f[7:0] = 0x55;
} r5;
};

View File

@@ -16,7 +16,7 @@
cpuif.write('h0, 'h00_F0);
// test hwenable + we
cb.hwif_in.r1.f.value <= 'hAB;
cb.hwif_in.r1.f.next <= 'hAB;
cb.hwif_in.r1.f.we <= '1;
@cb;
cb.hwif_in.r1.f.we <= '0;
@@ -40,7 +40,7 @@
cpuif.write('h0, 'hF0_00);
// test hwmask + we
cb.hwif_in.r2.f.value <= 'hAB;
cb.hwif_in.r2.f.next <= 'hAB;
cb.hwif_in.r2.f.we <= '1;
@cb;
cb.hwif_in.r2.f.we <= '0;
@@ -72,7 +72,7 @@
cpuif.assert_read('hC, 'h0F);
// test hwenable + we via reference
cb.hwif_in.r3.f.value <= 'hAA;
cb.hwif_in.r3.f.next <= 'hAA;
// toggle hwenable = 0F, we=1
cpuif.write('h0, 'h4_00_0F);
cpuif.write('h0, 'h0_00_00);
@@ -80,15 +80,26 @@
//---------------------------------
// test wel via reference
cb.hwif_in.r4.f.value <= 'hBB;
cb.hwif_in.r4.f.next <= 'hBB;
// toggle wel
cpuif.write('h0, 'h10_00_00);
cpuif.write('h0, 'h00_00_00);
cpuif.assert_read('h10, 'hBB);
cb.hwif_in.r4.f.value <= 'hCC;
cb.hwif_in.r4.f.next <= 'hCC;
// toggle wel
cpuif.write('h0, 'h10_00_00);
cpuif.write('h0, 'h00_00_00);
cpuif.assert_read('h10, 'hCC);
//---------------------------------
// test we and next via reference
cb.hwif_in.r5.f_next_value <= 'h54;
cpuif.assert_read('h14, 'h55);
cb.hwif_in.r5.f_next_value <= 'h56;
cb.hwif_in.r5.f_we <= '1;
@cb;
cb.hwif_in.r5.f_next_value <= '0;
cb.hwif_in.r5.f_we <= '0;
cpuif.assert_read('h14, 'h56);
{% endblock %}

View File

@@ -14,7 +14,7 @@
// Verify that hwif gets sampled at the same cycle as swacc strobe
counter = 'h10;
cb.hwif_in.r1.f.value <= counter;
cb.hwif_in.r1.f.next <= counter;
@cb;
event_count = 0;
fork
@@ -22,7 +22,7 @@
##0;
forever begin
counter++;
cb.hwif_in.r1.f.value <= counter;
cb.hwif_in.r1.f.next <= counter;
@cb;
if(cb.hwif_out.r1.f.swacc) begin
latched_data = counter;