bslathi19/PeakRDL-regblock
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Omit unecessary hwif signals if an external register is read-only or write-only. #58

Browse Source
This commit is contained in:
Alex Mykyta
2023-08-02 21:38:06 -07:00
parent 8a6f525ee2
commit 941871007b
10 changed files with 186 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
docs/rdl_features/external.rst
View File

@@ -44,10 +44,16 @@ hwif_out..req
When asserted, a read or write transfer will be initiated.
Qualifies all other request signals.
If a register is wide (``regwidth`` > ``accesswidth``), then the
If the register is wide (``regwidth`` > ``accesswidth``), then the
``hwif_out..req`` will consist of multiple bits, representing the access
strobe for each sub-word of the register.
If the register does not contain any readable fields, this strobe will be
suppressed for read operations.
If the register does not contain any writable readable fields, this strobe
will be suppressed for write operations.
hwif_out..req_is_wr
If ``1``, denotes that the current transfer is a write. Otherwise transfer is
a read.
@@ -59,11 +65,15 @@ hwif_out..wr_data
The bit-width of this signal always matches the CPUIF's bus width,
regardless of the regwidth.
If the register does not contain any writable fields, this signal is omitted.
hwif_out..wr_biten
Active-high bit-level write-enable strobes.
Only asserted bit positions will change the register value during a write
transfer.
If the register does not contain any writable fields, this signal is omitted.
Read Response
^^^^^^^^^^^^^
@@ -74,9 +84,13 @@ hwif_in..rd_ack
If the transfer is always completed in the same cycle, it is acceptable to
tie this signal to ``hwif_out..req && !hwif_out..req_is_wr``.
If the register does not contain any readable fields, this signal is omitted.
hwif_in..rd_data
Read response data.
If the register does not contain any readable fields, this signal is omitted.
Write Response
^^^^^^^^^^^^^^
hwif_in..wr_ack
@@ -85,6 +99,8 @@ hwif_in..wr_ack
If the transfer is always completed in the same cycle, it is acceptable to
tie this signal to ``hwif_out..req && hwif_out..req_is_wr``.
If the register does not contain any writable fields, this signal is omitted.
External Blocks