bslathi19/PeakRDL-regblock
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Omit unecessary hwif signals if an external register is read-only or write-only. #58

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This commit is contained in:
Alex Mykyta
2023-08-02 21:38:06 -07:00
parent 8a6f525ee2
commit 941871007b
10 changed files with 186 additions and 14 deletions
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22
src/peakrdl_regblock/addr_decode.py
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@@ -184,7 +184,16 @@ class DecodeLogicGenerator(RDLForLoopGenerator):
s = f"{self.addr_decode.get_access_strobe(node)} = {rhs};"
self.add_content(s)
if node.external:
self.add_content(f"is_external |= {rhs};")
readable = node.has_sw_readable
writable = node.has_sw_writable
if readable and writable:
self.add_content(f"is_external |= {rhs};")
elif readable and not writable:
self.add_content(f"is_external |= {rhs} & !cpuif_req_is_wr;")
elif not readable and writable:
self.add_content(f"is_external |= {rhs} & cpuif_req_is_wr;")
else:
raise RuntimeError
else:
# Register is wide. Create a substrobe for each subword
n_subwords = regwidth // accesswidth
@@ -194,7 +203,16 @@ class DecodeLogicGenerator(RDLForLoopGenerator):
s = f"{self.addr_decode.get_access_strobe(node)}[{i}] = {rhs};"
self.add_content(s)
if node.external:
self.add_content(f"is_external |= {rhs};")
readable = node.has_sw_readable
writable = node.has_sw_writable
if readable and writable:
self.add_content(f"is_external |= {rhs};")
elif readable and not writable:
self.add_content(f"is_external |= {rhs} & !cpuif_req_is_wr;")
elif not readable and writable:
self.add_content(f"is_external |= {rhs} & cpuif_req_is_wr;")
else:
raise RuntimeError
def exit_AddressableComponent(self, node: 'AddressableNode') -> None:
super().exit_AddressableComponent(node)