Omit unecessary hwif signals if an external register is read-only or write-only. #58

src/peakrdl_regblock/field_logic/generators.py

@@ -347,6 +347,8 @@ class FieldLogicGenerator(RDLForLoopGenerator):
             bslice = ""
 
         context = {
+            "has_sw_writable": node.has_sw_writable,
+            "has_sw_readable": node.has_sw_readable,
             "prefix": prefix,
             "strb": strb,
             "bslice": bslice,

src/peakrdl_regblock/field_logic/templates/external_reg.sv

@@ -5,13 +5,23 @@ always_ff {{get_always_ff_event(resetsignal)}} begin
     if({{get_resetsignal(resetsignal)}}) begin
         {{prefix}}.req <= '0;
         {{prefix}}.req_is_wr <= '0;
+    {%- if has_sw_writable %}
         {{prefix}}.wr_data <= '0;
         {{prefix}}.wr_biten <= '0;
+    {%- endif %}
     end else begin
+    {%- if has_sw_readable and has_sw_writable %}
         {{prefix}}.req <= {{strb}};
+    {%- elif has_sw_readable and not has_sw_writable %}
+        {{prefix}}.req <= !decoded_req_is_wr ? {{strb}} : '0;
+    {%- elif not has_sw_readable and has_sw_writable %}
+        {{prefix}}.req <= decoded_req_is_wr ? {{strb}} : '0;
+    {%- endif %}
         {{prefix}}.req_is_wr <= decoded_req_is_wr;
+    {%- if has_sw_writable %}
         {{prefix}}.wr_data <= decoded_wr_data{{bslice}};
         {{prefix}}.wr_biten <= decoded_wr_biten{{bslice}};
+    {%- endif %}
     end
 end
 
@@ -19,10 +29,18 @@ end
 {%- else -%}
 
 
+{%- if has_sw_readable and has_sw_writable %}
 assign {{prefix}}.req = {{strb}};
+{%- elif has_sw_readable and not has_sw_writable %}
+assign {{prefix}}.req = !decoded_req_is_wr ? {{strb}} : '0;
+{%- elif not has_sw_readable and has_sw_writable %}
+assign {{prefix}}.req = decoded_req_is_wr ? {{strb}} : '0;
+{%- endif %}
 assign {{prefix}}.req_is_wr = decoded_req_is_wr;
+{%- if has_sw_writable %}
 assign {{prefix}}.wr_data = decoded_wr_data{{bslice}};
 assign {{prefix}}.wr_biten = decoded_wr_biten{{bslice}};
+{%- endif %}
 
 
 {%- endif %}