Omit unecessary hwif signals if an external register is read-only or write-only. #58

2023-08-02 21:38:06 -07:00
parent 8a6f525ee2
commit 941871007b
10 changed files with 186 additions and 14 deletions
--- a/src/peakrdl_regblock/field_logic/generators.py
+++ b/src/peakrdl_regblock/field_logic/generators.py
@@ -347,6 +347,8 @@ class FieldLogicGenerator(RDLForLoopGenerator):
            bslice = ""

        context = {
+            "has_sw_writable": node.has_sw_writable,
+            "has_sw_readable": node.has_sw_readable,
            "prefix": prefix,
            "strb": strb,
            "bslice": bslice,