Omit unecessary hwif signals if an external register is read-only or write-only. #58

tests/run.sh

@@ -15,7 +15,7 @@ pip install -r $this_dir/requirements.txt
 
 # Install dut
 cd $this_dir/../
-python $this_dir/../setup.py install
+pip install -U .
 cd $this_dir
 
 # Run unit tests

tests/test_external/regblock.rdl

@@ -26,4 +26,26 @@ addrmap top {
         memwidth = 32;
         mementries = 8;
     } mm @ 0x3000;
+
+    reg my_ro_reg {
+        field {sw=r; hw=w;} whatever[32] = 0;
+    };
+    reg my_wo_reg {
+        field {sw=w; hw=r;} whatever[32] = 0;
+    };
+    external my_ro_reg ro_reg @ 0x4000;
+    external my_wo_reg wo_reg @ 0x4004;
+
+    reg my_wide_ro_reg {
+        regwidth = 64;
+        accesswidth = 32;
+        field {sw=r; hw=w;} whatever[32] = 0;
+    };
+    reg my_wide_wo_reg {
+        regwidth = 64;
+        accesswidth = 32;
+        field {sw=w; hw=r;} whatever[32] = 0;
+    };
+    external my_wide_ro_reg wide_ro_reg @ 0x4010;
+    external my_wide_wo_reg wide_wo_reg @ 0x4018;
 };

tests/test_external/tb_template.sv

@@ -95,6 +95,62 @@
         .rd_data(hwif_in.mm.rd_data),
         .wr_ack(hwif_in.mm.wr_ack)
     );
+
+    external_reg wo_reg_inst (
+        .clk(clk),
+        .rst(rst),
+
+        .req(hwif_out.wo_reg.req),
+        .req_is_wr(hwif_out.wo_reg.req_is_wr),
+        .wr_data(hwif_out.wo_reg.wr_data),
+        .wr_biten(hwif_out.wo_reg.wr_biten),
+        .rd_ack(),
+        .rd_data(),
+        .wr_ack(hwif_in.wo_reg.wr_ack)
+    );
+
+    external_reg ro_reg_inst (
+        .clk(clk),
+        .rst(rst),
+
+        .req(hwif_out.ro_reg.req),
+        .req_is_wr(hwif_out.ro_reg.req_is_wr),
+        .wr_data(32'b0),
+        .wr_biten(32'b0),
+        .rd_ack(hwif_in.ro_reg.rd_ack),
+        .rd_data(hwif_in.ro_reg.rd_data),
+        .wr_ack()
+    );
+
+    external_reg #(
+        .SUBWORDS(2)
+    ) wide_wo_reg_inst (
+        .clk(clk),
+        .rst(rst),
+
+        .req(hwif_out.wide_wo_reg.req),
+        .req_is_wr(hwif_out.wide_wo_reg.req_is_wr),
+        .wr_data(hwif_out.wide_wo_reg.wr_data),
+        .wr_biten(hwif_out.wide_wo_reg.wr_biten),
+        .rd_ack(),
+        .rd_data(),
+        .wr_ack(hwif_in.wide_wo_reg.wr_ack)
+    );
+
+    external_reg #(
+        .SUBWORDS(2)
+    ) wide_ro_reg_inst (
+        .clk(clk),
+        .rst(rst),
+
+        .req(hwif_out.wide_ro_reg.req),
+        .req_is_wr(hwif_out.wide_ro_reg.req_is_wr),
+        .wr_data(64'b0),
+        .wr_biten(64'b0),
+        .rd_ack(hwif_in.wide_ro_reg.rd_ack),
+        .rd_data(hwif_in.wide_ro_reg.rd_data),
+        .wr_ack()
+    );
 {%- endblock %}
 
 
@@ -161,6 +217,40 @@
         end
     end
 
+    repeat(20) begin
+        x = $urandom();
+        ro_reg_inst.value <= x;
+        cpuif.write('h4000, ~x);
+        cpuif.assert_read('h4000, x);
+        assert(ro_reg_inst.value == x);
+    end
+
+    repeat(20) begin
+        x = $urandom();
+        cpuif.write('h4004, x);
+        cpuif.assert_read('h4004, 0);
+        assert(wo_reg_inst.value == x);
+    end
+
+    for(int i=0; i<2; i++) begin
+        repeat(20) begin
+            x = $urandom();
+            wide_ro_reg_inst.value[i] <= x;
+            cpuif.write('h4010 + i*4, ~x);
+            cpuif.assert_read('h4010 + i*4, x);
+            assert(wide_ro_reg_inst.value[i] == x);
+        end
+    end
+
+    for(int i=0; i<2; i++) begin
+        repeat(20) begin
+            x = $urandom();
+            cpuif.write('h4018 + i*4, x);
+            cpuif.assert_read('h4018 + i*4, 0);
+            assert(wide_wo_reg_inst.value[i] == x);
+        end
+    end
+
     //--------------------------------------------------------------------------
     // Pipelined access
     //--------------------------------------------------------------------------