Add counter support
This commit is contained in:
Alex Mykyta
@@ -1,33 +1,4 @@
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================================================================================
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Overarching philosophy
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Encourage users to be able to tweak the design
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Templating:
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Design templates to be small bite-size snippets, each with clear intent
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Templates shall be extendable
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Templates shall be easy/intuitive
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Output:
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Output shall be beautiful. Consistent and clean formatting/whitespace builds trust
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Output has comments. Users will be looking at it.
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================================================================================
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On templating...
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Everything should be written out to a single file
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The only exception is if a struct port interface is used, then the appropriate
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struct package is also written out (or lumped into the same file?)
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Each layer should actually be its own separate template.
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Use helper functions to abstract away details about identifier implementation.
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Similarly, some fields will end up with additional port-level signals inferred.
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For example, if the user set the field's "anded=true" property
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the template would do something like:
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{{output_signal(field, "anded")}} = &{{field_value(field)}};
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Basically, i'd define a ton of helper functions that return the signal identifier.
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================================================================================
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Accesswidth vs Regwidth
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@@ -46,7 +17,7 @@ Changes to this tool this new understanding imposes:
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- derive the CPU bus width based on the largest regwidth
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this seems like a reasonable & easy thing to implement
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- CPUIF should make sure to always present an aligned address!
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if bus width is 32-bits, decoder logic shall recieve an address with bits [1:0] ALWAYS zeroed
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if bus width is 32-bits, decoder logic shall receive an address with bits [1:0] ALWAYS zeroed
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Codify this in the internal specification!
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- address decode may produce multiple strobes if registers are packed.
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Eg: if bus width is 32, and there is a region of 8-bit registers that are tightly packed,
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@@ -75,77 +46,49 @@ Write about this in the SystemRDL errata?
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Maybe not so much in other protocols...
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Maybe add some words to the "clarifications" section
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================================================================================
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Unit Testing
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I NEED to start building a suite of unit-tests!
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Goal:
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- Small easy-to-understand testcases
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- Parameterized testcases to rerun testcases with different cpuifs, etc.
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- coverage
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Split it into the following components:
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Common testbench SV infrastructure
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Make a generic SV framework that can be re-used everywhere
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Use SV interfaces/classes and even `include preprocessor tricks to make it possible
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to swap out for specific testcases:
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- cpuif abstraction layer
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Need to be able to swap out to different CPU interfaces easily
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- Clocks/resets
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- DUT instantiation
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Will need to account for minor variations in port list somehow
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Maybe a good time to use the .* method?
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- Helper functions, assertion library, etc.
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Testcase-specific
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SV sequence file that issues transactions and asserts things
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Dispatch tests completely through pytest
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- Each testcase has its own folder with:
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testcase-specific SV file(s)
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RDL file
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pytest entry point .py file
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- build up py utility functions that will:
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Export the testcase-specific RDL --> SV
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Compile and run the simulation
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need to deal with timeouts if the RTL deadlocks somehow. Limit of how many uS to run?
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Query sim result for pass/fail
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- Each testcase folder will likely have multiple subtests
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- Variations to RDL export:
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- different cpuif
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- pipe stages
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- etc.
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- Different test sequences
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may be necessary to test the same compilation in different ways
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I can imagine it may not be possible to do everything from a single test sequence.
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May require the sim to reset to T-0 for fresh-slate.
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- Handle these variations using pytest testcases & parameterizations as appropriate.
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Possibly something like:
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- Each pytest class --> unique compilation/elaboration
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pytest parameters to expand this for export variations
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- Each pytest class method --> simulation sequence
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- Collect coverage!
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install the tool in a venv, collect exporter coverage, etc.
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TBD if i want to deal with SV coverage (is that even allowed in modelsim free?)
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================================================================================
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Dev Todo list
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================================================================================
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- Signals - clean them up and add proper support
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Generate these in the hwif_in struct? I forget what I decided
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- FIXME: cpuif reset inside top-level addrmap results in two input signals:
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- one popped out to top
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- another inside the input struct
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- Interrupt properties
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i think my docs are missing a property or something...
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- Rework TB CPUIF driver a bit
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Split test API into a class
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class receives a vif to the driver
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make this more proper w.r.t extending stuff.
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- Add more CPUIF protocols
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- AXI-Lite
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- cpuif interface passthrough?
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- Add synthesis tests
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Create a new testcase base class
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Similar concept as before with testcases & parameterization.
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Launch Vivado and do out-of-context synthesis
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Override message severities to highlight:
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- undriven nets
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- multi-driven nets
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- combo loops
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Figure out a way to test these separately from other testcases
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maybe rearrange folders so:
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test/test_behav/...
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test/test_synth/...
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- break out 'next' and singlepulse into a separate section of their own.
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these should always be lowest priority regardless of precedence
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and always end up as the "else" clause in the conditional list.
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- Link more functions to the dereferencer
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I shouldn't have to go to the hwif or whatever
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dereferencer should have all the query functions
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- Start a sphinx docs thing
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I need to keep better track of everything!
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Diagrams of each layer in an architecture overview
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transcribe logbook into dev notes
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Define strict interface expectations for each layer!
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Including latency/etc
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endianness controls byte order of the CPU bus
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controls byteswap at the CPUIF layer
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Internally, use little endian ordering.
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@@ -155,16 +98,3 @@ endianness controls byte order of the CPU bus
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Do something about cpuif byte strobes?
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Remove for now?
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Demote to APB3?
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- Other field output assignments
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- HWIF layer
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- User Signals
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Generate these in the io struct? I forget what I decided
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- dereferencer has some remaining todos that depend on field logic
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- FIXME: cpuif reset inside top-level addrmap results in two input signals:
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- one popped out to top
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- another inside the input struct
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