Add counter support

test/lib/cpuifs/apb3/apb3_intf_driver.sv

@@ -91,9 +91,10 @@ interface apb3_intf_driver #(
         reset();
     endtask
 
-    task assert_read(logic [ADDR_WIDTH-1:0] addr, logic [DATA_WIDTH-1:0] expected_data);
+    task assert_read(logic [ADDR_WIDTH-1:0] addr, logic [DATA_WIDTH-1:0] expected_data, logic [DATA_WIDTH-1:0] mask = '1);
         logic [DATA_WIDTH-1:0] data;
         read(addr, data);
+        data &= mask;
         assert(data == expected_data) else $error("Read from 0x%x returned 0x%x. Expected 0x%x", addr, data, expected_data);
     endtask
 

test/lib/simulators/modelsim.py

@@ -9,6 +9,8 @@ class ModelSim(Simulator):
         cmd = [
             "vlog", "-sv", "-quiet", "-l", "build.log",
 
+            "+incdir+%s" % os.path.join(os.path.dirname(__file__), ".."),
+
             # Free version of ModelSim throws errors if generate/endgenerate
             # blocks are not used.
             # These have been made optional long ago. Modern versions of SystemVerilog do

test/lib/simulators/xilinx.py

@@ -8,13 +8,14 @@ class Xilinx(Simulator):
     """
     Don't bother using the Xilinx simulator... Its buggy and extraordinarily slow.
     As observed in v2021.1, clocking block assignments do not seem to actually simulate
-    correctly - assignemnt statements get ignored or the values get mangled.
+    correctly - assignment statements get ignored or the values get mangled.
 
     Keeping this here in case someday it works better...
     """
     def compile(self) -> None:
         cmd = [
-            "xvlog", "--sv"
+            "xvlog", "--sv",
+            "--include", os.path.join(os.path.dirname(__file__), ".."),
         ]
         cmd.extend(self.tb_files)
         subprocess.run(cmd, check=True)

test/lib/tb_base.sv

@@ -66,6 +66,7 @@ module tb;
         end
     end
 {%- endif %}
+    {% sv_line_anchor %}
 
     //--------------------------------------------------------------------------
     // Test Sequence
@@ -82,7 +83,7 @@ module tb;
             {%- endblock %}
             {%- endfilter %}
         end
-
+        {% sv_line_anchor %}
         ##5;
         $finish();
     end
@@ -90,7 +91,6 @@ module tb;
     //--------------------------------------------------------------------------
     // Monitor for timeout
     //--------------------------------------------------------------------------
-    {% sv_line_anchor %}
     initial begin
         ##{{cls.timeout_clk_cycles}};
         $fatal(1, "Test timed out after {{cls.timeout_clk_cycles}} clock cycles");