Add counter support

test/lib/simulators/modelsim.py

@@ -9,6 +9,8 @@ class ModelSim(Simulator):
         cmd = [
             "vlog", "-sv", "-quiet", "-l", "build.log",
 
+            "+incdir+%s" % os.path.join(os.path.dirname(__file__), ".."),
+
             # Free version of ModelSim throws errors if generate/endgenerate
             # blocks are not used.
             # These have been made optional long ago. Modern versions of SystemVerilog do

test/lib/simulators/xilinx.py

@@ -8,13 +8,14 @@ class Xilinx(Simulator):
     """
     Don't bother using the Xilinx simulator... Its buggy and extraordinarily slow.
     As observed in v2021.1, clocking block assignments do not seem to actually simulate
-    correctly - assignemnt statements get ignored or the values get mangled.
+    correctly - assignment statements get ignored or the values get mangled.
 
     Keeping this here in case someday it works better...
     """
     def compile(self) -> None:
         cmd = [
-            "xvlog", "--sv"
+            "xvlog", "--sv",
+            "--include", os.path.join(os.path.dirname(__file__), ".."),
         ]
         cmd.extend(self.tb_files)
         subprocess.run(cmd, check=True)