Add counter support

2021-12-11 20:41:49 -08:00
parent f5b12253ad
commit 9eddc9b60f
40 changed files with 1133 additions and 349 deletions
--- a/test/lib/simulators/modelsim.py
+++ b/test/lib/simulators/modelsim.py
@@ -9,6 +9,8 @@ class ModelSim(Simulator):
        cmd = [
            "vlog", "-sv", "-quiet", "-l", "build.log",

+            "+incdir+%s" % os.path.join(os.path.dirname(__file__), ".."),
+
            # Free version of ModelSim throws errors if generate/endgenerate
            # blocks are not used.
            # These have been made optional long ago. Modern versions of SystemVerilog do