Refactor readback mux implementation. Improves performance (#155) and eliminates illegal streaming operator usage (#165)
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@@ -38,18 +38,15 @@ This section also assigns any hardware interface outputs.
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Readback
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--------
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The readback layer aggregates and reduces all readable registers into a single
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read response. During a read operation, the same address decode strobes are used
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to select the active register that is being accessed.
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This allows for a simple OR-reduction operation to be used to compute the read
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data response.
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The readback layer aggregates and MUXes all readable registers into a single
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read response.
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For designs with a large number of software-readable registers, an optional
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fanin re-timing stage can be enabled. This stage is automatically inserted at a
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balanced point in the read-data reduction so that fanin and logic-levels are
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optimally reduced.
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.. figure:: diagrams/readback.png
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.. figure:: diagrams/rt-readback-fanin.png
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:width: 65%
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:align: center
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