bslathi19/PeakRDL-regblock
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Use clog2 helper function to improve clarity. #116

Browse Source
This commit is contained in:
Alex Mykyta
2024-12-19 19:47:41 -08:00
parent 80a46a082b
commit a15178c719
2 changed files with 4 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/peakrdl_regblock/field_logic/generators.py
View File

@@ -7,7 +7,7 @@ from systemrdl.node import RegNode, RegfileNode, MemNode, AddrmapNode
from ..struct_generator import RDLStructGenerator
from ..forloop_generator import RDLForLoopGenerator
from ..utils import get_indexed_path
from ..utils import get_indexed_path, clog2
from ..identifier_filter import kw_filter as kwf
if TYPE_CHECKING:
@@ -362,7 +362,7 @@ class FieldLogicGenerator(RDLForLoopGenerator):
def assign_external_block_outputs(self, node: 'AddressableNode') -> None:
prefix = "hwif_out." + get_indexed_path(self.exp.ds.top_node, node)
strb = self.exp.dereferencer.get_external_block_access_strobe(node)
addr_width = (node.size - 1).bit_length()
addr_width = clog2(node.size)
retime = False
if isinstance(node, RegfileNode):

3
src/peakrdl_regblock/hwif/generators.py
View File

@@ -6,6 +6,7 @@ from systemrdl.walker import WalkerAction
from ..struct_generator import RDLFlatStructGenerator
from ..identifier_filter import kw_filter as kwf
from ..sv_int import SVInt
from ..utils import clog2
if TYPE_CHECKING:
from systemrdl.node import Node, SignalNode, AddressableNode, RegfileNode
@@ -194,7 +195,7 @@ class OutputStructGenerator_Hier(HWIFStructGenerator):
def _add_external_block_members(self, node: 'AddressableNode') -> None:
self.add_member("req")
self.add_member("addr", (node.size - 1).bit_length())
self.add_member("addr", clog2(node.size))
self.add_member("req_is_wr")
self.add_member("wr_data", self.hwif.ds.cpuif_data_width)
self.add_member("wr_biten", self.hwif.ds.cpuif_data_width)