Use clog2 helper function to improve clarity. #116

src/peakrdl_regblock/field_logic/generators.py

@@ -7,7 +7,7 @@ from systemrdl.node import RegNode, RegfileNode, MemNode, AddrmapNode
 
 from ..struct_generator import RDLStructGenerator
 from ..forloop_generator import RDLForLoopGenerator
-from ..utils import get_indexed_path
+from ..utils import get_indexed_path, clog2
 from ..identifier_filter import kw_filter as kwf
 
 if TYPE_CHECKING:
@@ -362,7 +362,7 @@ class FieldLogicGenerator(RDLForLoopGenerator):
     def assign_external_block_outputs(self, node: 'AddressableNode') -> None:
         prefix = "hwif_out." + get_indexed_path(self.exp.ds.top_node, node)
         strb = self.exp.dereferencer.get_external_block_access_strobe(node)
-        addr_width = (node.size - 1).bit_length()
+        addr_width = clog2(node.size)
 
         retime = False
         if isinstance(node, RegfileNode):