Enable Vivado's xsim to run on some simpler testcases for better compile-check coverage. #7

tests/lib/sim_testcase.py

@@ -20,6 +20,8 @@ class SimTestCase(BaseTestCase):
 
     simulator_cls = SIM_CLS
 
+    tb_template_file = "tb_template.sv"
+
     @classmethod
     def _generate_tb(cls):
         """
@@ -41,7 +43,7 @@ class SimTestCase(BaseTestCase):
         }
 
         # template path needs to be relative to the Jinja loader root
-        template_path = os.path.join(cls.get_testcase_dir(), "tb_template.sv")
+        template_path = os.path.join(cls.get_testcase_dir(), cls.tb_template_file)
         template_path = os.path.relpath(template_path, template_root_path)
         template = jj_env.get_template(template_path)
 

tests/test_structural_sw_rw/testcase.py

@@ -1,8 +1,12 @@
+import os
+
 from parameterized import parameterized_class
 
 from ..lib.sim_testcase import SimTestCase
 from ..lib.synth_testcase import SynthTestCase
 from ..lib.test_params import TEST_PARAMS
+from ..lib.simulators.xilinx import Xilinx
+import pytest
 
 @parameterized_class(TEST_PARAMS)
 class Test(SimTestCase):
@@ -13,3 +17,24 @@ class Test(SimTestCase):
 class TestSynth(SynthTestCase):
     def test_dut(self):
         self.run_synth()
+
+
+@pytest.mark.skipif(os.environ.get("STUB_SIMULATOR", False), reason="user skipped")
+@parameterized_class(TEST_PARAMS)
+class TestVivado(SimTestCase):
+    """
+    Vivado XSIM's implementation of clocking blocks is broken, which is heavily used
+    by the testbench infrastructure in most testcases.
+    Since this group of tests does not rely on writing HWIF values, the bugs in
+    xsim are avoided.
+
+    Run this testcase using xsim to get some cross-simulator coverage.
+    Goal is to validate the generated RTL doesn't use constructs that offend xsim.
+
+    This is skipped in CI stub tests as it doesn't add value
+    """
+
+    simulator_cls = Xilinx
+
+    def test_dut(self):
+        self.run_test()