From a7cea87d4057da3362d7d7c9da2dd29a11bacd41 Mon Sep 17 00:00:00 2001 From: Maciej Dudek Date: Tue, 9 Apr 2024 23:14:17 +0200 Subject: [PATCH] Remove unreachable code According to the SystemRDL specification interrupt can be either: level, posedge, negedge, bothedge, or nonsticky. This means that it's impossible to reach create filed that satisfies [Pos|Neg|Both]edgeNonstickybit match functions. Signed-off-by: Maciej Dudek --- src/peakrdl_regblock/field_logic/__init__.py | 3 - .../field_logic/hw_interrupts.py | 65 +------------------ 2 files changed, 1 insertion(+), 67 deletions(-) diff --git a/src/peakrdl_regblock/field_logic/__init__.py b/src/peakrdl_regblock/field_logic/__init__.py index 4abe41d..2136383 100644 --- a/src/peakrdl_regblock/field_logic/__init__.py +++ b/src/peakrdl_regblock/field_logic/__init__.py @@ -447,9 +447,6 @@ class FieldLogic: self.add_hw_conditional(hw_interrupts.PosedgeStickybit(self.exp), AssignmentPrecedence.HW_WRITE) self.add_hw_conditional(hw_interrupts.NegedgeStickybit(self.exp), AssignmentPrecedence.HW_WRITE) self.add_hw_conditional(hw_interrupts.BothedgeStickybit(self.exp), AssignmentPrecedence.HW_WRITE) - self.add_hw_conditional(hw_interrupts.PosedgeNonsticky(self.exp), AssignmentPrecedence.HW_WRITE) - self.add_hw_conditional(hw_interrupts.NegedgeNonsticky(self.exp), AssignmentPrecedence.HW_WRITE) - self.add_hw_conditional(hw_interrupts.BothedgeNonsticky(self.exp), AssignmentPrecedence.HW_WRITE) self.add_hw_conditional(hw_interrupts.Sticky(self.exp), AssignmentPrecedence.HW_WRITE) self.add_hw_conditional(hw_interrupts.Stickybit(self.exp), AssignmentPrecedence.HW_WRITE) self.add_hw_conditional(hw_write.WEWrite(self.exp), AssignmentPrecedence.HW_WRITE) diff --git a/src/peakrdl_regblock/field_logic/hw_interrupts.py b/src/peakrdl_regblock/field_logic/hw_interrupts.py index 85d4446..dbebdd3 100644 --- a/src/peakrdl_regblock/field_logic/hw_interrupts.py +++ b/src/peakrdl_regblock/field_logic/hw_interrupts.py @@ -2,7 +2,7 @@ from typing import TYPE_CHECKING, List from systemrdl.rdltypes import InterruptType -from .bases import NextStateConditional, NextStateUnconditional +from .bases import NextStateConditional if TYPE_CHECKING: from systemrdl.node import FieldNode @@ -160,66 +160,3 @@ class BothedgeStickybit(NextStateConditional): f"next_c = {R} | ({Iq} ^ {I});", "load_next_c = '1;", ] - -class PosedgeNonsticky(NextStateUnconditional): - """ - Positive edge non-stickybit - """ - comment = "posedge nonsticky" - unconditional_explanation = "Edge-sensitive non-sticky interrupts always update the field state" - def is_match(self, field: 'FieldNode') -> bool: - return ( - field.is_hw_writable - and not field.get_property('stickybit') - and field.get_property('intr type') == InterruptType.posedge - ) - - def get_assignments(self, field: 'FieldNode') -> List[str]: - I = self.exp.hwif.get_input_identifier(field) - Iq = self.exp.field_logic.get_next_q_identifier(field) - return [ - f"next_c = ~{Iq} & {I};", - "load_next_c = '1;", - ] - -class NegedgeNonsticky(NextStateUnconditional): - """ - Negative edge non-stickybit - """ - comment = "negedge nonsticky" - unconditional_explanation = "Edge-sensitive non-sticky interrupts always update the field state" - def is_match(self, field: 'FieldNode') -> bool: - return ( - field.is_hw_writable - and not field.get_property('stickybit') - and field.get_property('intr type') == InterruptType.negedge - ) - - def get_assignments(self, field: 'FieldNode') -> List[str]: - I = self.exp.hwif.get_input_identifier(field) - Iq = self.exp.field_logic.get_next_q_identifier(field) - return [ - f"next_c = {Iq} & ~{I};", - "load_next_c = '1;", - ] - -class BothedgeNonsticky(NextStateUnconditional): - """ - edge-sensitive non-stickybit - """ - comment = "bothedge nonsticky" - unconditional_explanation = "Edge-sensitive non-sticky interrupts always update the field state" - def is_match(self, field: 'FieldNode') -> bool: - return ( - field.is_hw_writable - and not field.get_property('stickybit') - and field.get_property('intr type') == InterruptType.bothedge - ) - - def get_assignments(self, field: 'FieldNode') -> List[str]: - I = self.exp.hwif.get_input_identifier(field) - Iq = self.exp.field_logic.get_next_q_identifier(field) - return [ - f"next_c = {Iq} ^ {I};", - "load_next_c = '1;", - ]