diff --git a/README.md b/README.md
index 3aef6c4..058f982 100644
--- a/README.md
+++ b/README.md
@@ -3,7 +3,7 @@
 [![PyPI - Python Version](https://img.shields.io/pypi/pyversions/peakrdl-regblock.svg)](https://pypi.org/project/peakrdl-regblock)
 
 # PeakRDL-regblock
-Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
+Compile SystemRDL into a SystemVerilog control/status register (CSR) block
 
 ## Documentation
 See the [PeakRDL-regblock Documentation](http://peakrdl-regblock.readthedocs.io) for more details
diff --git a/docs/index.rst b/docs/index.rst
index 9f67b50..67f86c0 100644
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -10,6 +10,7 @@ your hardware design.
 * Options for many popular CPU interface protocols (AMBA APB, AXI4-Lite, and more)
 * Configurable pipelining options for designs with fast clock rates.
 * Broad support for SystemRDL 2.0 features
+* Fully synthesizable SystemVerilog. Tested on Xilinx/AMD's Vivado & Intel Quartus
 
 
 
diff --git a/setup.py b/setup.py
index f944e90..1770447 100644
--- a/setup.py
+++ b/setup.py
@@ -15,7 +15,7 @@ setuptools.setup(
     version=version,
     author="Alex Mykyta",
     author_email="amykyta3@github.com",
-    description="Convert SystemRDL into SystemVerilog RTL that implements a register block",
+    description="Compile SystemRDL into a SystemVerilog control/status register (CSR) block",
     long_description=long_description,
     long_description_content_type="text/markdown",
     url="https://github.com/SystemRDL/PeakRDL-regblock",