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Simulator compatibility updates

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This commit is contained in:
Alex Mykyta
2023-10-22 20:43:34 -07:00
parent d689bb7077
commit b5b1ba790e
29 changed files with 244 additions and 111 deletions
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8
tests/test_structural_sw_rw/tb_template.sv
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@@ -71,13 +71,13 @@
cpuif.assert_read('h3000, 'h4DEAB000);
// rw_reg_lsb0
`ifndef XSIM
// Xilinx simulator has poor support for streaming operators. Skip
`ifndef XILINX_XSIM
// Skip due to xsim bug simulating internal RTL - bitswap inside conditional corrupts data
cpuif.assert_read('h3004, 0);
cpuif.write('h3004, 'h4DEAB000);
@cb;
assert({<<{cb.hwif_out.rw_reg_lsb0.f1.value}} == 8'hAB);
assert({<<{cb.hwif_out.rw_reg_lsb0.f2.value}} == 11'h4DE);
assert(`bitswap(cb.hwif_out.rw_reg_lsb0.f1.value) == 8'hAB);
assert(`bitswap(cb.hwif_out.rw_reg_lsb0.f2.value) == 11'h4DE);
cpuif.assert_read('h3004, 'h4DEAB000);
`endif
{% endblock %}