Simulator compatibility updates

This commit is contained in:
Alex Mykyta
2023-10-22 20:43:34 -07:00
parent d689bb7077
commit b5b1ba790e
29 changed files with 244 additions and 111 deletions

View File

@@ -69,7 +69,7 @@
assert(cb.hwif_out.reg1_msb0.f1.value == 0);
cpuif.write('hE, 'hDEF1);
@cb; @cb;
assert({<<{cb.hwif_out.reg1_msb0.f1.value}} == 64'hDEF19ABC56781234);
assert(`bitswap(cb.hwif_out.reg1_msb0.f1.value) == 64'hDEF19ABC56781234);
cpuif.assert_read('h8, 'h1234);
cpuif.assert_read('hA, 'h5678);
cpuif.assert_read('hC, 'h9ABC);
@@ -104,8 +104,8 @@
assert(cb.hwif_out.reg2_msb0.f2.value == 0);
cpuif.write('h16, 'hAA12);
@cb; @cb;
assert({<<{cb.hwif_out.reg2_msb0.f1.value}} == 12'h234);
assert({<<{cb.hwif_out.reg2_msb0.f2.value}} == 4'h1);
assert(`bitswap(cb.hwif_out.reg2_msb0.f1.value) == 12'h234);
assert(`bitswap(cb.hwif_out.reg2_msb0.f2.value) == 4'h1);
cpuif.assert_read('h14, 'h3400);
cpuif.assert_read('h16, 'h0012);
@@ -281,7 +281,7 @@
cpuif.assert_read('hA, 'h0200);
cpuif.assert_read('hC, 'h0070);
cpuif.assert_read('hE, 'h0002);
assert({<<{cb.hwif_out.reg1_msb0.f1.value}} == 'h0002_0070_0200_A000);
assert(`bitswap(cb.hwif_out.reg1_msb0.f1.value) == 'h0002_0070_0200_A000);
// Check that strobes are cumulative
cpuif.write('h8, 'h0030, 'h00F0);
@@ -297,7 +297,7 @@
cpuif.assert_read('hA, 'h0278);
cpuif.assert_read('hC, 'hA07D);
cpuif.assert_read('hE, 'hAF02);
assert({<<{cb.hwif_out.reg1_msb0.f1.value}} == 'hAF02_A07D_0278_A230);
assert(`bitswap(cb.hwif_out.reg1_msb0.f1.value) == 'hAF02_A07D_0278_A230);
{% endblock %}

View File

@@ -2,6 +2,8 @@ from ..lib.sim_testcase import SimTestCase
from ..lib.cpuifs.passthrough import Passthrough
class Test(SimTestCase):
incompatible_sim_tools = {"xsim"} # due to cb struct assignment bug
cpuif = Passthrough() # test with bit strobes
def test_dut(self):