Add simulation-time width assertions to SV interfaces. #128

src/peakrdl_regblock/cpuif/apb4/__init__.py

@@ -2,6 +2,7 @@ from ..base import CpuifBase
 
 class APB4_Cpuif(CpuifBase):
     template_path = "apb4_tmpl.sv"
+    is_interface = True
 
     @property
     def port_declaration(self) -> str:
@@ -12,6 +13,8 @@ class APB4_Cpuif(CpuifBase):
 
 
 class APB4_Cpuif_flattened(APB4_Cpuif):
+    is_interface = False
+
     @property
     def port_declaration(self) -> str:
         lines = [

src/peakrdl_regblock/cpuif/apb4/apb4_tmpl.sv

@@ -1,3 +1,15 @@
+{%- if cpuif.is_interface -%}
+`ifndef SYNTHESIS
+    initial begin
+        assert($bits({{cpuif.signal("paddr")}}) >= {{ds.package_name}}::{{ds.module_name.upper()}}_MIN_ADDR_WIDTH)
+            else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits({{cpuif.signal("paddr")}}), {{ds.package_name}}::{{ds.module_name.upper()}}_MIN_ADDR_WIDTH);
+        assert($bits({{cpuif.signal("pwdata")}}) == {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH)
+            else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits({{cpuif.signal("pwdata")}}), {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH);
+    end
+`endif
+
+{% endif -%}
+
 // Request
 logic is_active;
 always_ff {{get_always_ff_event(cpuif.reset)}} begin